Patents by Inventor Young-Ho Na

Young-Ho Na has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143211
    Abstract: In an embodiment of the disclosed technology, since a host device manages data stored in a storage device on the basis of a zone corresponding to a storage block of the storage device, the load of the storage device may be reduced, and the operation efficiency of the storage device may be increased by the control of the host device. Therefore, it is possible to improve the performance of a computing system including the host device and the storage device.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 2, 2024
    Inventors: Hyeong Ju NA, Jin Woo KIM, Young Ho AHN, Yoon Won LEE
  • Patent number: 11970090
    Abstract: A railess variable seatback type rear seat includes: a linear movement device configured to convert a rotation of a motor into a linear movement; a sliding movement device configured to convert the linear movement into a sliding movement in which a seat cushion is pushed forward or backward; and a reclining angle change device configured to convert the sliding movement into a reclining movement, and to fold a seatback, which is connected to the seat cushion, forward or to recline the seatback backward.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: April 30, 2024
    Assignees: HYUNDAI MOTOR COMPANY, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.
    Inventors: Seung-Hyun Kim, Sang-Hyun Lee, Min-Ju Lee, Byung-Yong Choi, Chan-Ho Jung, Seon-Chae Na, Young-Woon Choi, Jae-Jin Lee, Dong-Hwan Kim, In-Chang Hwang
  • Patent number: 10811107
    Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Ho Na, Young Sun Min, Dae Seok Byeon
  • Publication number: 20200273528
    Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.
    Type: Application
    Filed: August 5, 2019
    Publication date: August 27, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young Ho NA, Young Sun Min, Dae Seok Byeon
  • Patent number: 10692543
    Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Ho Na, Young-Sun Min, Dae-Seok Byeon
  • Publication number: 20200105308
    Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.
    Type: Application
    Filed: March 25, 2019
    Publication date: April 2, 2020
    Inventors: YOUNG-HO NA, YOUNG-SUN MIN, DAE-SEOK BYEON
  • Patent number: 10089386
    Abstract: Provided is a method of providing an answer keyword, the method including: obtaining at least one of a search word history including a first inquiry search word of a certain domain pre-received from first user terminals, and webpage information selected by the first user terminals from a search result according to the search word history; extracting answer candidate keywords regarding the first inquiry search word from at least one of the search word history and the webpage information based on keyword lists of the certain domain; calculating a relation between the first inquiry search word and each of the extracted answer candidate keywords; and when the first inquiry search word is received from a second user terminal, transmitting answer keywords for the first inquiry search word, which are selected from the answer candidate keywords based on the relation, to the second user terminal.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 2, 2018
    Assignee: NAVER Corporation
    Inventors: Joong Sun Lim, In Jae Sung, Hannuri Ha, Young Ho Na
  • Publication number: 20160350408
    Abstract: Provided is a method of providing an answer keyword, the method including: obtaining at least one of a search word history including a first inquiry search word of a certain domain pre-received from first user terminals, and webpage information selected by the first user terminals from a search result according to the search word history; extracting answer candidate keywords regarding the first inquiry search word from at least one of the search word history and the webpage information based on keyword lists of the certain domain; calculating a relation between the first inquiry search word and each of the extracted answer candidate keywords; and when the first inquiry search word is received from a second user terminal, transmitting answer keywords for the first inquiry search word, which are selected from the answer candidate keywords based on the relation, to the second user terminal.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 1, 2016
    Inventors: Joong Sun Lim, In Jae Sung, Hannuri Ha, Young Ho Na
  • Patent number: 7450218
    Abstract: A scanner of photolithographic equipment has a reticle masking device capable of forming an aperture, in the shape of a slit, without inducing vibrations in the scanner. The reticle masking device forms the slit electronically, without the use of motive power, and can likewise vary the width of the slit in a direction parallel to the direction of movement of a reticle stage. In particular, the width of the slit is increase at the beginning and decreased at the end of a scan. Preferably, the reticle masking device is a liquid crystal display. It is thus possible to isolate and compensate for vibrations induced by the movement of the reticle stage or wafer stage during a scan, and thus to prevent flaws in the exposure process due to relative positional errors and thereby enhance the production yield.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: November 11, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Ho Na
  • Publication number: 20060268252
    Abstract: A scanner of photolithographic equipment has a reticle masking device capable of forming an aperture, in the shape of a slit, without inducing vibrations in the scanner. The reticle masking device forms the slit electronically, without the use of motive power, and can likewise vary the width of the slit in a direction parallel to the direction of movement of a reticle stage. In particular, the width of the slit is increase at the beginning and decreased at the end of a scan. Preferably, the reticle masking device is a liquid crystal display. It is thus possible to isolate and compensate for vibrations induced by the movement of the reticle stage or wafer stage during a scan, and thus to prevent flaws in the exposure process due to relative positional errors and thereby enhance the production yield.
    Type: Application
    Filed: May 22, 2006
    Publication date: November 30, 2006
    Inventor: Young-Ho Na