Abstract: A semiconductor package includes a first substrate. A second substrate is spaced apart from the first substrate. A semiconductor chip is between the first substrate and the second substrate. The semiconductor chip is electrically connected to the second substrate. A molding layer surrounds the semiconductor chip. A plate directly contacts a bottom surface of the semiconductor chip. A heat transfer structure connects the plate and the first substrate to each other.

Abstract: A semiconductor package includes a base substrate, a first chip on the base substrate, a second chip on the first chip, a molding film extending around the first chip and the second chip, a redistribution layer on an upper surface of the molding film, and a plurality of outer posts that are on side surfaces of at least one of the first chip or the second chip, are electrically connected to the base substrate and the redistribution layer, and extend into the molding film, where the first chip or the second chip includes: a signal pad through which one or more electrical signals are transmitted, and a thermal pad configured to dissipate heat away from the semiconductor package, and where the plurality of outer posts include a signal post electrically connected to the signal pad or a thermal post electrically connected to the thermal pad.

Abstract: A semiconductor package includes a package substrate, a first structure including a first chip on the package substrate, a first wiring post connected to the first chip, and a first molding layer surrounding the first chip and the first wiring post, and a second structure including a second chip on the package substrate, a second wiring post connected to the second chip, and a second molding layer surrounding the second chip and the second wiring post. The second structure includes a block in a portion of an area over the package substrate and including a first molding portion surrounding the second chip and the second wiring post, a second molding portion in a remaining area over the package substrate, and a boundary portion positioned between the second molding portion and a block surface located at a lateral side of the first molding portion facing the second molding portion.

Abstract: According to some embodiments, a semiconductor package may include a first semiconductor chip; a second semiconductor chip disposed on a first semiconductor chip; a wall structure disposed on the first semiconductor chip and spaced apart from the second semiconductor chip in a first direction; and a mold layer covering the first and second semiconductor chips, wherein the first semiconductor chip includes a transceiver disposed thereon and spaced apart from the second semiconductor chip, the mold layer has an opening exposing the transceiver, the wall structure is disposed in the opening and is in contact with an inner wall of the mold layer exposed to the opening, the mold layer has a first height, and the wall structure has a second height smaller than the first height.

Abstract: A method of manufacturing a semiconductor package includes estimating an error in a solder ball attaching process, determining a specification of a ball tool and a method of the solder ball attaching process, based on the estimated error, manufacturing the ball tool according to the determined specification thereof, and performing the solder ball attaching process based on the method of the solder ball attaching process. The determining of the specification of the ball tool and the method of the solder ball attaching process includes determining a number of a plurality of holders in the ball tool and a position and a width of each of the plurality of holders, determining a number of a plurality of working regions of a substrate and a position and a width of each of the plurality of working regions, and dividing a substrate into the plurality of working regions.

Abstract: An apparatus for mounting solder balls comprises a stage to support a substrate thereon, a mounting unit to mount solder balls on the substrate, and a solder ball mask between the mounting unit and the substrate. The solder ball mask includes a first face facing the substrate and a second face opposite to the first face. The solder ball mask has inner surfaces defining through-holes extending through a thickness of the solder ball mask from the second face to the first face. The apparatus causes the solder balls to move through separate, respective through-holes. Each of the through-holes includes a first opening defined in the first face and a second opening defined in the second face. A first spacing between adjacent first openings of the plurality of through-holes is different from a second spacing between adjacent second openings of the through-holes.

Abstract: A semiconductor package includes a substrate having a vent hole defined therein. Semiconductor chips are mounted on an upper surface of the substrate. Chip connection terminals are disposed between the substrate and the semiconductor chips. Substrate connection terminals are disposed on a lower surface of the substrate. A plated layer includes a vertical heat-dissipation layer on an inner wall of the vent hole, a first heat-dissipation layer on the upper surface of the substrate and connected to at least one of the chip connection terminals and a second heat-dissipation layer on the lower surface of the substrate and connected to at least one of the substrate connection terminals. An encapsulant covers the upper surface of the substrate, the chip connection terminals, and the semiconductor chips, and fills a space between the semiconductor chips and the substrate. The encapsulant is on the plated layer and fills the vent hole.

Abstract: A semiconductor package includes a first substrate. A second substrate is spaced apart from the first substrate. A semiconductor chip is between the first substrate and the second substrate. The semiconductor chip is electrically connected to the second substrate. A molding layer surrounds the semiconductor chip. A plate directly contacts a bottom surface of the semiconductor chip. A heat transfer structure connects the plate and the first substrate to each other.

Abstract: An adsorption device for a reflow process according to an embodiment is coupled to a semiconductor package to form a reflow assembly in a reflow process. The semiconductor package includes a substrate and a semiconductor chip disposed at one surface of the substrate. The adsorption device for the reflow process includes a main body and a pressure control member. The main body includes an inner space portion and includes a bottom portion and a substrate adsorption portion that protrudes from the bottom portion to be adhered to the one surface of the substrate in an outer region of the semiconductor chip by a negative pressure. The pressure control member maintains a pressure of the inner space portion.

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

Abstract: An apparatus for mounting solder balls comprises a stage to support a substrate thereon, a mounting unit to mount solder balls on the substrate, and a solder ball mask between the mounting unit and the substrate. The solder ball mask includes a first face facing the substrate and a second face opposite to the first face. The solder ball mask has inner surfaces defining through-holes extending through a thickness of the solder ball mask from the second face to the first face. The apparatus causes the solder balls to move through separate, respective through-holes. Each of the through-holes includes a first opening defined in the first face and a second opening defined in the second face. A first spacing between adjacent first openings of the plurality of through-holes is different from a second spacing between adjacent second openings of the through-holes.

Abstract: A method of manufacturing a semiconductor package includes estimating an error in a solder ball attaching process, determining a specification of a ball tool and a method of the solder ball attaching process, based on the estimated error, manufacturing the ball tool according to the determined specification thereof, and performing the solder ball attaching process based on the method of the solder ball attaching process. The determining of the specification of the ball tool and the method of the solder ball attaching process includes determining a number of a plurality of holders in the ball tool and a position and a width of each of the plurality of holders, determining a number of a plurality of working regions of a substrate and a position and a width of each of the plurality of working regions, and dividing a substrate into the plurality of working regions.

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

Abstract: Provided is a method of fabricating a semiconductor package. The method includes providing a substrate including a plurality of semiconductor chips; forming a mold layer covering the semiconductor chips; forming a first shielding layer on the mold layer; cutting the mold layer and the first shielding layer to form trenches between the semiconductor chips; and forming a second shielding layer to fill the trenches.

Abstract: A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads.

Abstract: Provided is a method of fabricating a semiconductor package. The method includes providing a substrate including a plurality of semiconductor chips; forming a mold layer covering the semiconductor chips; forming a first shielding layer on the mold layer; cutting the mold layer and the first shielding layer to form trenches between the semiconductor chips; and forming a second shielding layer to fill the trenches.

Abstract: A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads.

Abstract: A method of fabricating a semiconductor device comprises loading a circuit board including a semiconductor chip into underfill equipment, positioning the circuit board on a depositing chuck of the underfill equipment, filling an underfill material in a space between the semiconductor chip and the circuit board placed on the depositing chuck; transferring the circuit board including the underfill material so that it is positioned on a post-treatment chuck of the underfill equipment; heating the underfill material of the circuit board placed on the post-treatment chuck in a vacuum state, and unloading the circuit board, of which the underfill material has been heated in the vacuum state, from the underfill equipment.

Abstract: The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon.

Abstract: The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon.