Abstract: Provided is an electronic device, including a first chiplet including a first bus interface, a first interconnect management module, and a first interconnect module, and a second chiplet connected to the first chiplet through the first interconnect module, wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores, in a register, first information associated with the request transaction.

Abstract: Provided is an electronic device, in which a first management module of a first chiplet generates a first request transaction for measuring a latency between the first chiplet and a second chiplet, and transmits the generated first request transaction to the second chiplet through a first interconnect module of the first chiplet, a second management module of the second chiplet generates a first response transaction corresponding to the first request transaction, and transmits the generated first response transaction to the first chiplet through a second interconnect module of the second chiplet, and the latency between the first chiplet and the second chiplet is determined based on a first time at which the first request transaction is generated in the first chiplet and a second time at which the first chiplet receives the first response transaction.

Abstract: Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.

Abstract: Provided is an electronic device, including a first chiplet including a first bus interface, a first interconnect management module, and a first interconnect module, and a second chiplet connected to the first chiplet through the first interconnect module, wherein, in response to an occurrence of a request transaction associated with the second chiplet, the first interconnect management module stores, in a register, first information associated with the request transaction.

Abstract: Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and a save and forward module connected to the interconnect module and the bus interface, in which the save and forward module includes a slave port that receives a transaction from one of the interconnect module or the bus interface, a data buffer that temporarily stores at least a portion of the transaction, and a master port that transmits the transaction stored in the data buffer to the other one of the interconnect module or the bus interface, and the transaction is divided into predetermined units and transmitted.

Abstract: Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and an address remapper block connected to the interconnect module and the bus interface, in which the address remapper block receives a transaction and remaps a destination address in the transaction.

Abstract: An electronic device comprising a plurality of chiplets is disclosed. The electronic device comprises a first chiplet that generates a transaction, a second chiplet that receives the transaction, and at least one third chiplet that relays the transaction, wherein the first chiplet determines a route path for the transaction that passes through the at least one third chiplet, and transmits the transaction through the determined route path for the transaction.

Abstract: The present disclosure relates to a method for communicating between chiplets in a chiplet system. The chiplet system includes a first chiplet and a second chiplet, and the method includes, by the first chiplet, generating a die-to-die interface flit from a first protocol type transaction based on conversion information, by the first chiplet, transmitting the die-to-die interface flit to the second chiplet, and, by the second chiplet, generating a second protocol type transaction from the die-to-die interface flit based on the conversion information.

Abstract: The present disclosure relates to a method for communicating between chiplets in a chiplet system. The chiplet system includes a first chiplet and a second chiplet, the first chiplet includes a controller including a protocol layer, and the method includes, by the protocol layer of the first chiplet, receiving first data, by the protocol layer of the first chiplet, receiving conversion information from the second chiplet, and, by the protocol layer of the first chiplet, generating second data based on the received first data and conversion information.

Abstract: A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.

Abstract: A data processing system includes a controller and a computation device. The controller receives a request for processing a neural network computation from a host, the request including an input feature map and a weight filter. The computation device includes a storage unit allocated to each of integration groups, and performs a convolution operation on the input feature map and the weight filter, sequentially outputs pooling elements as a result of the convolution operation, and performs a pooling operation on the pooling elements. The pooling elements corresponds to each integration group. The computation device performs the pooling operation by integrating a pooling value read from the storage unit and each of the pooling elements into a single value and updating the pooling value stored in the storage unit with a result of the integrating. The integrating and the updating are repeated until all of the pooling elements are integrated.

Abstract: A data processing system includes a controller configured to receive a neural network operation processing request from a host device; and an in-memory computing device including a plurality of processing elements. The in-memory computing device is configured to receive an input feature map and a weight filter from the controller, and perform a neural network operation in the plurality of processing elements based on the weight filter and a plurality of division maps generated from the input feature map, wherein the in-memory computing device performs the neural network operation by not moving a reused element, which is operated at least twice among elements constituting the division maps during the neural network operation, between the processing elements.

Abstract: A memory device performs a convolution operation. The memory device includes first to N-th processing elements (PEs), a first analog-to-digital converter (ADC), a first shift adder, and a first accumulator. The first to N-th PEs, where N is a natural number equal to or greater than 2, are respectively associated with at least one weight data included in a weight feature map and are configured to perform a partial convolution operation with at least one input data included in an input feature map. The first ADC is configured to receive a first partial convolution operation result from the first to N-th PEs. The first shift adder shifts an output of the first ADC. The first accumulator accumulates an output from the first shift adder.

Abstract: Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.

Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a temperature monitor device configured to count values that vary according to operation statuses of memory devices; a status check device configured to output status information of the memory devices based on the count values; and a scheduler configured to store the status information according to arrangements of the memory devices, and output the status information in response to a request received from a host.

Abstract: A neural network computation apparatus includes a first processing block including a plurality of processing units that each perform a matrix multiplication operation on input data and weights, and a second processing block including a plurality of element-wise operation processing groups. The element-wise operation processing group selectively perform a first neural network computation operation and a second neural network computation operation. The first neural network computation operation comprises the matrix multiplication operation on the input data and the weights and an activation operation on a result value of the matrix multiplication operation, and the second neural network computation operation comprises an activation operation on the result value of the matrix multiplication operation, which is transferred from the first processing block, and an element-wise operation.

Abstract: A memory controller includes a temperature monitor configured to update temperature states of a memory device divided into groups as temperature scores and a scheduler configured to update a command score using the temperature scores and change a priority of the command score to match with a current operation mode.

Abstract: A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.

Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a temperature monitor device configured to count values that vary according to operation statuses of memory devices; a status check device configured to output status information of the memory devices based on the count values; and a scheduler configured to store the status information according to arrangements of the memory devices, and output the status information in response to a request received from a host.

Abstract: A memory system includes a memory module comprising a plurality of memory devices, and a memory controller suitable for controlling the plurality of memory devices to perform a refresh operation or performing an error correction code (ECC) operation on the plurality of memory devices, according to a refresh operation request.