Abstract: An capacitor processing apparatus, and a method for processing a capacitor, may include a clamping module grabbing or releasing a capacitor to transport the capacitor, and processing modules matched with each other to process and test leads of the capacitor, and simultaneously perform various processes through different processing units formed in the processing modules. These various processes may include separating, bending, and cutting the leads of the capacitor. The testing and processing provided by the current invention make it is possible to process a larger amount of capacitors assembled to a capacitor assembly, and to identify and remove defective capacitors before assembly.

Abstract: An operation method of a terminal in a mobile communication system may comprise: determining whether prediction of a communication failure is needed while performing communication with a base station; in response to determining that prediction of the communication failure is required, performing a communication failure prediction procedure; and in response to predicted occurrence of the communication failure according to a result of performing the communication failure prediction procedure, performing a recovery procedure for the predicted communication failure.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: The present invention relates to a method and apparatus for controlling and configuring a guide robot system for correction and evaluation of walking posture. A method of analyzing and evaluating gait according to an embodiment of the present disclosure may comprise: projecting a guide footprint at a pre-configured point based on a user's walking direction; measuring a user's footprint in walking performed by a user based on a position of the guide footprint; and performing analysis and evaluation of the user's footprint based on the guide footprint.

Abstract: An apparatus for assembling a capacitor assembly and a method for assembling the capacitor assembly using the same according to the present disclosure includes: a processing module mechanically, electrically coupling a capacitor to a bracket to assemble to a capacitor assembly, a test module testing whether the assembled capacitor assembly normally operates, and a conveyor module in which the capacitor assembly is arranged to sequentially perform the processing and test processes while moving in one direction, and it is possible to precisely detect whether the capacitor assembly is defective through two or more tests, and if many mechanical defects occur, it is possible to reduce the possibility of occurrence of the mechanical defect by controlling and adjusting some of the processing modules and improve productivity.

Abstract: A curable composition is provided. The curable composition can eliminate or minimize the generation of bubbles inside the cured product after the initiation reaction of the curable monomer, prevent expansion of a material when used to encapsulate a device, and provide a uniform cured product to solve the problem of separation between the upper and lower substrates bonded together, thereby improving device encapsulation performance.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

Abstract: An apparatus and a method for processing a capacitor according to the present disclosure may include a clamping module grabbing or releasing a capacitor to transport the capacitor, and a first processing module and a second processing module matched with each other to process and test leads of the capacitor, and simultaneously perform various processes through different processing units formed in the first processing module and symmetrical processing units formed in the second processing module and corresponding to be matched with the processing units. By providing the apparatus and method for processing the capacitor, it is possible to process a larger amount of capacitors assembled to a capacitor assembly and identify and remove the electrical defect before assembled to the assembly.

Abstract: An apparatus for assembling a capacitor assembly and a method for assembling the capacitor assembly using the same according to the present disclosure includes: a processing module mechanically, electrically coupling a capacitor to a bracket to assemble to a capacitor assembly, a test module testing whether the assembled capacitor assembly normally operates, and a conveyor module in which the capacitor assembly is arranged to sequentially perform the processing and test processes while moving in one direction, and it is possible to precisely detect whether the capacitor assembly is defective through two or more tests, and if many mechanical defects occur, it is possible to reduce the possibility of occurrence of the mechanical defect by controlling and adjusting some of the processing modules and improve productivity.

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.