Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

Abstract: An image processing method is provided, including obtaining an input image, generating a distance field image including distance values by calculating each of the distance values respectively corresponding to pixels of the obtained input image, and enlarging the input image using the generated distance field image, wherein the generating of the distance field image includes, with respect to each pixel of the input image, determining each pixel as a center pixel and determining pixels at a constant distance away from the center pixel as reference pixels, calculating a shortest distance from among distances between the center pixel and reference pixels indicating an edge among the reference pixels, and determining the calculated shortest distance as a distance value corresponding to each pixel.

Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern.

Abstract: An image processing method is provided, including obtaining an input image, generating a distance field image including distance values by calculating each of the distance values respectively corresponding to pixels of the obtained input image, and enlarging the input image using the generated distance field image, wherein the generating of the distance field image includes, with respect to each pixel of the input image, determining each pixel as a center pixel and determining pixels at a constant distance away from the center pixel as reference pixels, calculating a shortest distance from among distances between the center pixel and reference pixels indicating an edge among the reference pixels, and determining the calculated shortest distance as a distance value corresponding to each pixel.

Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern.

Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

Abstract: An image data scaling method is disclosed. The image data scaling method includes generating a depth map including depth information for each of a plurality of areas of a 3-dimensional (3D) image frame constituting image data, setting a scale ratio in each area of the 3D image frame based on the generated depth map, scaling the 3D image frame based on the set scale ratio, and outputting the scaled 3D image frame.

Abstract: The present invention relates to a dye for a dye-sensitized solar cell. The dye according to the present invention has a high degree of light absorbency and can improve the photoelectric current conversion efficiency when employed in a light-absorbing layer for a solar cell. Chemical Formula 1 illustrates the present invention. wherein X1, X2, N, Z1, and A1 are described herein.

Abstract: Vertical memory devices include a channel, a ground selection line (GSL), a word line, a string selection line (SSL), a pad and an etch-stop layer. The channel extends in a first direction on a substrate. The channel includes an impurity region and the first direction is perpendicular to a top surface of the substrate. At least one GSL, a plurality of the word lines and at least one SSL are spaced apart from each other in the first direction on a sidewall of the channel. The pad is disposed on a top surface of the channel. The etch-stop layer contacts the pad.

Abstract: The present invention relates to a dye for a dye-sensitised solar cell. The dye according to the present invention has a high degree of light absorbency and can improve the photoelectric current conversion efficiency when employed in a light-absorbing layer for a solar cell.

Abstract: An apparatus to suppress artifacts in an image signal. The apparatus includes a differential value calculation unit to calculate a differential value between adjacent pixels with respect to an input image signal, a diffusion amount calculation unit to calculate an amount of diffusion between the adjacent pixels on the basis of the differential value calculated by the differential value calculation unit, and a pixel value conversion unit to convert the present pixel value of the image signal inputted on the basis of the diffusion amount between the pixels calculated by the diffusion amount calculation unit. The apparatus changes the pixel value in consideration of the differential value between the adjacent pixels, and thus it can provide a high quality image signal without losing or misrecognizing the artifacts of the image signal.

Abstract: A method and an apparatus for controlling a power of a display device including a backlight, and a display device having a power controlling function are provided. The apparatus includes: a histogram analyzer that analyzes a histogram of an input image signal including one or more color components, and determines an intensity clipping based on the analyzed histogram; an image brightness compensation unit that calculates an intensity increasing ratio of the input image signal using the intensity clipping, and applies the intensity increasing ratio to each of the color components to generate an output image signal, an intensity of which is increased; and a backlight brightness controller that controls a brightness of the backlight based on the intensity increasing ratio.

Abstract: An apparatus and method of processing shoot artifacts of an image signal includes a maximum gradient value calculation part to set a window of a predetermined size based on a current pixel of an input image signal and to calculate a maximum gradient value based on values of pixels in the window, a limit value calculation part to calculate a limit value corresponding to the maximum gradient value, a dilation amount calculation part to calculate a dilation amount corresponding to the current pixel based on the calculated limit value and a pixel difference between the current pixel neighboring pixels of the current pixel, and a pixel value conversion part to add a current pixel value to a value obtained by multiplying the calculated dilation amount by a predetermined gain value.