Patents by Inventor Young-Jin Kwon

Young-Jin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12362108
    Abstract: An capacitor processing apparatus, and a method for processing a capacitor, may include a clamping module grabbing or releasing a capacitor to transport the capacitor, and processing modules matched with each other to process and test leads of the capacitor, and simultaneously perform various processes through different processing units formed in the processing modules. These various processes may include separating, bending, and cutting the leads of the capacitor. The testing and processing provided by the current invention make it is possible to process a larger amount of capacitors assembled to a capacitor assembly, and to identify and remove defective capacitors before assembly.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: July 15, 2025
    Assignee: Samwha Electric Co. Ltd.
    Inventors: Jong On Park, Tae Yun Kim, Eun Kyun Joo, Young Jin Kwon, Jang Yong Yoon, Ji Heon Choi, Long Ji Li
  • Publication number: 20250119969
    Abstract: An operation method of a terminal in a mobile communication system may comprise: determining whether prediction of a communication failure is needed while performing communication with a base station; in response to determining that prediction of the communication failure is required, performing a communication failure prediction procedure; and in response to predicted occurrence of the communication failure according to a result of performing the communication failure prediction procedure, performing a recovery procedure for the predicted communication failure.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 10, 2025
    Inventors: Hyun Seo PARK, Young Jin KWON, Yunjoo KIM, Seungjae BAHNG, Jungbo SON, Anseok LEE, Yu Ro LEE, Sung Cheol CHANG, Heesoo LEE
  • Patent number: 12218062
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: February 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Hyoung Kim, Young-Jin Kwon, Geun Won Lim
  • Publication number: 20240415412
    Abstract: The present invention relates to a method and apparatus for controlling and configuring a guide robot system for correction and evaluation of walking posture. A method of analyzing and evaluating gait according to an embodiment of the present disclosure may comprise: projecting a guide footprint at a pre-configured point based on a user's walking direction; measuring a user's footprint in walking performed by a user based on a position of the guide footprint; and performing analysis and evaluation of the user's footprint based on the guide footprint.
    Type: Application
    Filed: May 2, 2024
    Publication date: December 19, 2024
    Inventors: Young Jin KWON, Jae Chul KIM
  • Patent number: 12040134
    Abstract: An apparatus for assembling a capacitor assembly and a method for assembling the capacitor assembly using the same according to the present disclosure includes: a processing module mechanically, electrically coupling a capacitor to a bracket to assemble to a capacitor assembly, a test module testing whether the assembled capacitor assembly normally operates, and a conveyor module in which the capacitor assembly is arranged to sequentially perform the processing and test processes while moving in one direction, and it is possible to precisely detect whether the capacitor assembly is defective through two or more tests, and if many mechanical defects occur, it is possible to reduce the possibility of occurrence of the mechanical defect by controlling and adjusting some of the processing modules and improve productivity.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: July 16, 2024
    Assignee: Samwha Electric Co. Ltd.
    Inventors: Jong On Park, Tae Yun Kim, Eun Kyun Joo, Young Jin Kwon, Jin Ho Kim, Geun Ju Cha, Chan Ser Jeon
  • Publication number: 20240117084
    Abstract: A curable composition is provided. The curable composition can eliminate or minimize the generation of bubbles inside the cured product after the initiation reaction of the curable monomer, prevent expansion of a material when used to encapsulate a device, and provide a uniform cured product to solve the problem of separation between the upper and lower substrates bonded together, thereby improving device encapsulation performance.
    Type: Application
    Filed: September 11, 2023
    Publication date: April 11, 2024
    Inventors: Young Jin KWON, Seong Chan SON, Jin Wuk KIM, Dong Min KIM, Ja Hun BYEON
  • Publication number: 20240088045
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Jun Hyoung KIM, Young-Jin KWON, Geun Won LIM
  • Patent number: 11903206
    Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Seon Ahn, Ji Sung Cheon, Young Jin Kwon, Seok Cheon Baek, Woong Seop Lee
  • Patent number: 11862566
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 2, 2024
    Inventors: Jun Hyoung Kim, Young-Jin Kwon, Geun Won Lim
  • Publication number: 20230328989
    Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gi Yong CHUNG, Ho Jin KIM, Young-Jin KWON, Dong Seog EUN
  • Publication number: 20230292515
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 14, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan SON, Kohji KANAMORI, Shin-Hwan KANG, Young Jin KWON
  • Patent number: 11716849
    Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: August 1, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gi Yong Chung, Ho Jin Kim, Young-Jin Kwon, Dong Seog Eun
  • Patent number: 11696442
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
  • Publication number: 20220392715
    Abstract: An apparatus and a method for processing a capacitor according to the present disclosure may include a clamping module grabbing or releasing a capacitor to transport the capacitor, and a first processing module and a second processing module matched with each other to process and test leads of the capacitor, and simultaneously perform various processes through different processing units formed in the first processing module and symmetrical processing units formed in the second processing module and corresponding to be matched with the processing units. By providing the apparatus and method for processing the capacitor, it is possible to process a larger amount of capacitors assembled to a capacitor assembly and identify and remove the electrical defect before assembled to the assembly.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 8, 2022
    Applicant: Samwha Electric Co., Ltd.
    Inventors: Jong On PARK, Tae Yun KIM, Eun Kyun JOO, Young Jin KWON, Jang Yong YOON, Ji Heon CHOI, Long Ji LI
  • Publication number: 20220375698
    Abstract: An apparatus for assembling a capacitor assembly and a method for assembling the capacitor assembly using the same according to the present disclosure includes: a processing module mechanically, electrically coupling a capacitor to a bracket to assemble to a capacitor assembly, a test module testing whether the assembled capacitor assembly normally operates, and a conveyor module in which the capacitor assembly is arranged to sequentially perform the processing and test processes while moving in one direction, and it is possible to precisely detect whether the capacitor assembly is defective through two or more tests, and if many mechanical defects occur, it is possible to reduce the possibility of occurrence of the mechanical defect by controlling and adjusting some of the processing modules and improve productivity.
    Type: Application
    Filed: June 15, 2021
    Publication date: November 24, 2022
    Applicant: Samwha Electric Co., Ltd.
    Inventors: Jong On PARK, Tae Yun KIM, Eun Kyun JOO, Young Jin KWON, Jin Ho KIM, Geun Ju CHA, Chan Ser JEON
  • Publication number: 20220278125
    Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Inventors: Jong Seon AHN, Ji Sung CHEON, Young Jin KWON, Seok Cheon BAEK, Woong Seop LEE
  • Patent number: 11342351
    Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Seon Ahn, Ji Sung Cheon, Young Jin Kwon, Seok Cheon Baek, Woong Seop Lee
  • Publication number: 20210335811
    Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.
    Type: Application
    Filed: January 7, 2021
    Publication date: October 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gi Yong CHUNG, Ho Jin KIM, Young-Jin KWON, Dong Seog EUN
  • Publication number: 20210210431
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Application
    Filed: September 11, 2020
    Publication date: July 8, 2021
    Inventors: Jun Hyoung KIM, Young-Jin KWON, Geun Won LIM
  • Patent number: D1011294
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 16, 2024
    Assignee: Samwha Electric Co., Ltd.
    Inventors: Jong On Park, Tae Yun Kim, Eun Kyun Joo, Young Jin Kwon, Won Seop Song