Abstract: An embodiment composition for solid electrolyte membranes of all-solid-state batteries includes a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities. An embodiment method of manufacturing a solid electrolyte membrane for an all-solid-state battery includes forming a composition including a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities and cross-linking the composition.

Abstract: Aspects of the disclosure provide for eliminating or reducing uniquification of blocks in a chip-level graph of a computer chip, to reduce the size of the graph while still encoding block-specific information. For each group of blocks in the graph generated from a multiply-instantiated block (MIB), a block in the group is selected as a base block. The physical position of the base block is encoded in a reduced graph, and the physical positions of the remaining blocks are encoded as a linear transformation of the physical position of the base block across the face of the chip. Each group of blocks instantiated from the same MIB is represented as a single instance. The reduced graph can be fed into a device configured to perform a circuit component placement process, to identify the placement of circuit components for blocks in the chip in accordance with one or more objectives.

Abstract: A substrate treating apparatus of the present disclosure comprises: a chamber member having an accommodation space configured to accommodate a vessel part where a substrate treatment region constituting a supercritical treatment space are formed, and an opening configured to move the substrate inside or outside; a shutter configured to open or close the chamber member; and a first exhaust part configured to discharge an internal air from the accommodation space to the outside, wherein the temperature of the substrate treatment region is increased.

Abstract: A battery pack is provided including at least one rechargeable secondary battery; a battery frame having a battery accommodation portion configured to accommodate the at least one secondary battery; a packaging member provided in the form of an adhesion sheet having an adhesive surface formed at one surface thereof, the packaging member including a body portion fixedly adhered to an upper portion of the secondary battery accommodated in the battery frame and a fixing portion bent and extended downward from the body portion and having the adhesive surface fixedly adhered to an outer surface of an outermost edge of the battery frame; and an anti-noise member attached to at least one portion of the adhesive surface of the packaging member.

Abstract: An apparatus for controlling a discharge pressure of a fluid includes: a pump configured to suck the fluid through an inlet or to discharge the sucked fluid through an outlet; a distributor connected to the pump and to an injection nozzle provided by a sensor and configured to distribute the fluid discharged from the pump to the sensor; and a controller. The controller is configured to control the pump to operate selectively in accordance with detection of contamination of the sensor and to control operation of the distributor to be forcibly delayed during operation of the pump such that the fluid distributed to the sensor, when detected as being contaminated, is controlled to reach a selected required discharge pressure of different required discharge pressures selected in accordance with water amount information and a degree of contamination of the sensor.

Abstract: The present invention relates to a VOC reduction system and a VOC reduction method that applies pulse type thermal energy to a catalyst to activate the catalyst and oxidizes and removes the VOC.

Abstract: A multilayer capacitor includes a body including a stack structure in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and disposed on the body to be respectively connected to the at least one first internal electrode and the at least one second internal electrode, wherein each of the first and second external electrodes includes a first conductive layer including a first conductive material and glass; and an oxide layer including an oxide and disposed on at least a portion of an external surface of the first conductive layer.

Abstract: A fluid level measurement system using a buoyant body includes a guide part installed in a direction perpendicular to the bottom surface of a fluid storage tank, and provided with a space in which a fluid can move therein; a buoyant body inserted into the guide part, and configured to float along the surface of the fluid inside the guide part; and a measurement part coupled to the top end of the guide part, and configured to measure the level of the surface of the fluid inside the fluid storage tank by transmitting a signal toward the buoyant body in the inner space of the guide part and then receiving a signal reflected from the buoyant body.

Abstract: Ophthalmic therapeutic agents having as pharmaceutically active ingredient a poorly water soluble drug of formula 1 are described. Specifically, an ophthalmic formulation containing an inclusion complex of a poorly soluble drug of formula 1 enclosed in cyclodextrin or a cyclodextrin derivative in an aqueous solution of pH 10 or higher is administered to a patient in need of optic nerve protection.

Abstract: Aspects of the disclosure are directed to automatically determining floor planning in chips, which factors in memory macro alignment. A deep reinforcement learning (RL) agent can be trained to determine optimal placements for the memory macros, where memory macro alignment can be included as a regularization cost to be added to the placement objective as a RL reward. Tradeoffs between the placement objective and alignment of macros can be controlled by a tunable alignment parameter.

Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.

Abstract: The present invention relates to electrode slurry coating apparatus and method, the present invention ultimately allowing the process efficiency to be increased and rate of errors to be reduced when double-layer structured active material layers are formed by temporally adjusting the height of first and second discharge outlets through which active material is discharged.

Abstract: Proposed are a substrate processing apparatus and a substrate processing method capable of efficiently preventing contamination of a substrate and a processing space caused by a reverse flow of purge gas.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: A tablet form of an epoxy resin composition for encapsulation of semiconductor elements, where the tablet form of the epoxy resin composition: (i) includes 97 wt % or more of tablets having a diameter of 0.1 mm to less than 2.8 mm and a height of 0.1 mm to less than 2.8 mm, as measured using an ASTM standard sieve; (ii) satisfies the following Equation 1, ? ? ? D × ? ? ? H ? ? ? D + ? ? ? H ? 1.0 , where ?D is a standard deviation of tablet diameters and ?H is a standard deviation of tablet heights, as measured with respect to 50 tablets arbitrarily selected from the tablets; and (iii) the tablets have a compression density of 1.2 g/mL to 1.7 g/mL.

Abstract: A tableted epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the tableted epoxy resin composition, the tableted epoxy resin composition satisfying the following conditions (i) a proportion of tablets of the tableted epoxy resin composition having a diameter of greater than or equal to 0.1 mm and less than 2.8 mm and a height of greater than or equal to 0.1 mm and less than 2.8 mm is about 97 wt % or more, as measured by sieve analysis using ASTM standard sieves; (ii) the tablets have a packed density of greater than about 1.7 g/mL; and (iii) a ratio of packed density to cured density of the tablets is about 0.6 to about 0.87.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.