Abstract: According to various embodiments of the disclosure, an antenna device comprises: a first antenna array including an array of a plurality of first radiation patches, a communication circuit configured to transmit and/or receive a radio signal using at least one of the first radiation patches, and at least one first isolator comprising a conductor disposed in an area between two adjacent first radiation patches among the first radiation patches. The first isolator may include a first portion, a second portion disposed in parallel with the first portion, and a third portion electrically connecting the first portion with the second portion. The first portion and the second portion may be configured to generate current flows having a phase difference of 180 degrees with respect to each other.

Abstract: The invention generally relates to a method of providing random access for video data in which a P-frame of the video data is configured to be random accessible in addition to I-frames. More specifically, the invention relates to a method of providing random access for video data in which a P-frame is configured to be random accessible based on a random access reference frame which is provided via a separate channel such as header area of video data packets or a metadata file, whereby the random access for video data may be effectively provided with overcoming the conventional video random access technology depending on the I-frame only. The invention makes it possible to configure a P-frame random accessible simply by accompanying a random access reference frame of small datasize, whereby video compression ratio may be improved due to smaller numbers of I-frames being included in video data than conventional arts.

Abstract: The present invention relates to a caching method of multi-core graphic processing unit (GPU) for improving image processing performance by efficiently storing video data into the cache memory out of the global memory. One aspect of the present invention is to provide a caching method of graphic processing unit (GPU) having multiple cores wherein at least a part of pixels out of A*B pixels of video data are cached into a cache memory in order to perform image processing on k pixels of N*N size (where, k, N, A and B are natural numbers; k=N*N; A>N; B>N), the method comprising: grouping the at least a part of pixels out of A*B pixels into k pixel groups; mapping the k pixel groups to k cores of the GPU one-to-one basis by utilizing index information of each of the k pixels; and storing video data of the k pixel groups in the cache memory with reference to the mapping result.

Abstract: The invention generally relates to a method of providing random access for video data in which a P-frame of the video data is configured to be random accessible in addition to I-frames. More specifically, the invention relates to a method of providing random access for video data in which a P-frame is configured to be random accessible based on a random access reference frame which is provided via a separate channel such as header area of video data packets or a metadata file, whereby the random access for video data may be effectively provided with overcoming the conventional video random access technology depending on the I-frame only. The invention makes it possible to configure a P-frame random accessible simply by accompanying a random access reference frame of small datasize, whereby video compression ratio may be improved due to smaller numbers of I-frames being included in video data than conventional arts.

Abstract: The present invention relates to a caching method of multi-core graphic processing unit (GPU) for improving image processing performance by efficiently storing video data into the cache memory out of the global memory. One aspect of the present invention is to provide a caching method of graphic processing unit (GPU) having multiple cores wherein at least a part of pixels out of A*B pixels of video data are cached into a cache memory in order to perform image processing on k pixels of N*N size (where, k, N, A and B are natural numbers; k=N*N; A>N; B>N), the method comprising: grouping the at least a part of pixels out of A*B pixels into k pixel groups; mapping the k pixel groups to k cores of the GPU one-to-one basis by utilizing index information of each of the k pixels; and storing video data of the k pixel groups in the cache memory with reference to the mapping result.