Patents by Inventor Youngjun Cheon

Youngjun Cheon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20230180477
    Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun YANG, Bio KIM, Yujin KIM, Kyong-won AN, Sookyeom YONG, Junggeun LEE, Youngjun CHEON
  • Three-dimensional semiconductor memory devices
    Patent number: 11569261
    Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 31, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun Yang, Bio Kim, Yujin Kim, Kyong-Won An, Sookyeom Yong, Junggeun Jee, Youngjun Cheon
  • THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20200395381
    Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun YANG, Bio KIM, Yujin KIM, Kyong-Won AN, Sookyeom YONG, Junggeun JEE, Youngjun CHEON
  • Three-dimensional semiconductor memory devices
    Patent number: 10797074
    Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun Yang, Bio Kim, Yujin Kim, Kyong-Won An, Sookyeom Yong, Junggeun Jee, Youngjun Cheon
  • THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    Publication number: 20200091186
    Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first stack structure on a substrate including a cell array region and a connection region, a second stack structure on the first stack structure, a first vertical channel hole penetrating the first stack structure and partially exposing the substrate and a bottom surface of the second stack structure, on the cell array region, a second vertical channel hole penetrating the second stack structure and exposing the first vertical channel hole, on the cell array region, a bottom diameter of the second vertical channel hole being smaller than an top diameter of the first vertical channel hole, and a buffer pattern placed in the first vertical channel hole and adjacent to the bottom surface of the second stack structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: March 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jaehyun YANG, Bio Kim, Yujin Kim, Kyong-Won An, Sookyeom Yong, Junggeun Jee, Youngjun Cheon