Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Abstract: A mobile communication system controls transmission power of radio links between a base station and a mobile station. The mobile communication system comprises (a) assigning forward and reverse dedicated control channels to the base station and the mobile station, respectively, and controlling transmission power of the forward and reverse dedicated control channels so that the respective channels can receive data; (b) discontinuing the transmission power control, when data to transmit/receive is not generated for a predetermined time; and ĉ for power level arbitration, re-controlling the transmission power of the forward and reverse dedicated control channels in a state where the transmission power control is not performed, so as to adjust the transmission power with which the data can be received.

Abstract: A device and method are provided for reducing the peak-to-average power ratio of a mobile station's transmit power in a mobile communication system by spreading and modulating the transmission data by a complex spreading sequence. The complex spreading sequence is generated to have a plurality of chips and a phase difference of 90° between every two successive complex chips in response to each chip of a PN (Pseudo Noise) sequence. The device and method flexibly control the mobile transmit power by limiting its peak-to-average power ratio to a specific range and thus confining the mobile transmit power to a linear characteristic portion in a characteristic curve of a power amplifier. The phase of the complex spreading sequence is prevented from shifting by 180° (i.e., &pgr;) to maintain the mobile transmit power in the linear portion of the power amplifier characteristic curve.