Abstract: A battery module includes a sub-module stack formed by stacking a plurality of sub-modules including a cooling member having a coolant flow path and a plurality of battery cells disposed on both surfaces of the cooling member; and a pair of bus bar frame assemblies coupled to one side and the other side of the sub-module stack to electrically connect the plurality of battery cells.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

Abstract: An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing costs is provided. The organic light emitting diode display includes: a substrate, a transistor on the substrate, and an organic light emitting diode (OLED) connected to the transistor, wherein the transistor includes a semiconductor member on the substrate, an insulating member on the semiconductor member, a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and a gate electrode on the insulating member, wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

Abstract: An organic light emitting diode display having a lightly doped region formed in a transistor for simplifying manufacturing process and reducing manufacturing costs is provided. The organic light emitting diode display includes: a substrate, a transistor on the substrate, and an organic light emitting diode (OLED) connected to the transistor, wherein the transistor includes a semiconductor member on the substrate, an insulating member on the semiconductor member, a source member and a drain member disposed on the semiconductor member and respectively disposed at opposite sides of the insulating member, and a gate electrode on the insulating member, wherein each of the source member and the drain member includes a plurality of layers having different impurity doping concentrations.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a substrate; a plurality of transistors formed on the substrate; and a light-emitting device connected to the plurality of transistors, wherein the transistor includes a gate electrode, the plurality of transistors include a first transistor and a second transistor of which lateral wall slope angles of the gate electrode are different from each other, and the first transistor further includes a doping control member formed on a lateral wall of the gate electrode.

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A thin film transistor and a display device having the thin film transistor capable of reducing the voltage between the source and drain electrodes of the thin film transistor are disclosed. One inventive aspect includes a gate electrode, a semiconductor pattern, a source electrode and a drain electrode. The source and drain electrodes are formed on the semiconductor pattern and spaced apart from each other. At least one of the source electrode and the drain electrode does not overlap the gate electrode.

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.

Abstract: A display substrate includes a base substrate, a switching element, a gate line, a data line and a pixel electrode. Each of the gate line and the data line includes a first metal layer, and a second metal layer directly on the first metal layer. The switching element is on the base substrate, and includes a control electrode and an input electrode or an output electrode. The control electrode includes the first metal layer and excludes the second metal layer, and extends from the gate line. The input electrode or the output electrode includes a second metal layer and excludes the first metal layer. The input electrode extends from the data line. The pixel electrode is electrically connected to the output electrode of the switching element through a first contact hole, and includes a transparent conductive layer.

Abstract: Provided is a thin film transistor array panel. A thin film transistor array panel according to an exemplary embodiment includes a gate wire having a first region where the gate line is disposed, and a second region where the gate electrode is disposed, and a thickness of the gate wire formed in the first region is greater than the thickness of the gate wire that is formed in the second region.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process for field stop of the high voltage transistor ion implantation process and a mask removal process.

Abstract: A method of manufacturing a NAND flash device which can improve uniformity of disturb fail characteristics by performing an annealing process after an ion implantation process for forming a P well, reduce a fail bit count by performing an annealing process after an ion implantation process for controlling a threshold voltage and before a process for forming a high voltage gate oxide film, and prevent disturb fail by omitting an STI ion implantation process in a cell region.

Abstract: A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.

Abstract: Disclosed is a method of manufacturing a high voltage transistor in a flash memory device. The method can prohibit a punch leakage current of an isolation film while satisfying active characteristics of the high voltage transistor without the need for a mask process for field stop of the high voltage transistor ion implantation process and a mask removal process.