Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.

Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Abstract: A semiconductor package includes: a semiconductor chip including a body having a first surface and a second surface, opposing the first surface, a connection pad disposed on the first surface of the body, and an extension pad disposed on the connection pad; and a connection structure including an insulating layer disposed on the first surface of the body of the semiconductor chip, a redistribution via penetrating through the insulating layer and having one side thereof in contact with the extension pad, and a redistribution layer disposed on the insulating layer and having a via pad in contact with the other side of the redistribution via, wherein a horizontal cross-sectional area of extension pad of the semiconductor chip is greater than a horizontal cross-sectional area of the connection pad of the semiconductor chip.

Abstract: A printed circuit board and a manufacturing method thereof. The manufacturing method of the printed circuit board includes: coating a first solder resist on an upper surface of a substrate having a circuit pattern formed thereon; removing the first solder resist in the remaining portion except a first specific area by performing primary development after exposing the substrate coated with the first solder resist; coating a second solder resist, which has different properties from the first solder resist, on the upper surface of the substrate having the first solder resist remaining in the first specific area; and removing the second solder resist in the remaining portion except a second specific area by performing secondary development after exposing the substrate coated with the second solder resist.

Abstract: Disclosed is a method of manufacturing a printed circuit board for a semiconductor package, which minimizes or completely obviates masking work upon the plating of each pad for the surface treatment of a printed circuit board for a semiconductor package, thereby simplifying the overall process and increasing the mounting reliability.

Abstract: In a method of inspecting an identification mark, an image of the identification mark on a semiconductor wafer is obtained. The identification mark may be identified using the identification mark image. A region where the identification mark is formed may be inspected using the identification mark image after the identification mark is identified.

Abstract: A method and apparatus of classifying repetitive defects on a substrate is provided. Defects of dies on the substrate are sequentially compared with a predetermined reference die. Sets of coordinates are marked on the reference die which are corresponding to the position of the defects on the dies on the substrate. Then, repetitive defects are classified which are repeatedly marked in a specified region on the reference die.

Abstract: In a method of classifying directional defects on an object straight lines are drawn from any defect among all defects on the object toward adjacent defects. At least three defects that are positioned within an allowable angle from the straight lines are classified as directional defects. Thus, only the directional defects among all the defects on the semiconductor substrate may be accurately classified after performing a chemical mechanical polishing (CMP) process, so that the CMP process may be effectively managed.

Abstract: In a method of classifying defects, actual information with respect to actual defects by each of processes on an object on which the processes are sequentially carried out is obtained. The actual information is accumulated in sequence of the processes to obtain composite information by each of the processes with respect to entire defects that are generated in preceding processes. Added information with respect to defects, which are generated only in each of the processes, among the actual defects is obtained by each of the processes based on the actual information and the composite information. The added information contains information with respect to the defects generated only in each of the processes so that the detected defects may be accurately classified as defects generated in any one among the processes based on the added information.

Abstract: A method and apparatus of classifying repetitive defects on a substrate is provided. Defects of dies on the substrate are sequentially compared with a predetermined reference die. Sets of coordinates are marked on the reference die which are corresponding to the position of the defects on the dies on the substrate. Then, repetitive defects are classified which are repeatedly marked in a specified region on the reference die.

Abstract: A method of aligning a substrate can comprise primarily aligning the substrate having a pattern, obtaining pattern information corresponding to a configuration of the pattern, comparing the pattern information with predetermined reference pattern information to corroborate the acceptability of the pattern information, selectively exchanging the predetermined reference pattern information with the pattern information based on the acceptability of the pattern information, and secondarily aligning the substrate to correlate the position of the pattern with the pattern information.

Abstract: A method and an apparatus for examining wafers includes a wafer cassette having a capacity for holding a plurality of wafers located on each of first and second locaters. The wafer cassettes are fixedly held on the first and second locaters during the wafer examination. A first indicator shows that the wafer cassettes are fixedly held on the first and second locaters. A robot arm sequentially carries each of the wafers between the first locator, an aligner, a scanning chamber and the second locater to examine the wafers. The wafer cassettes are released when the examination is complete, and a second indicator shows that the examination is complete.