Abstract: A light emitting display apparatus includes a gate driver including stages provided in a substrate and a plurality of gate lines connected to the stages. Each of the stages includes a shift register and two buffers connected to the shift register, a first buffer of two buffers configuring an nth stage and a first shift register configuring the nth stage are provided in an nth horizontal portion and a second buffer of the two buffers is provided in an n+2th horizontal portion, a third buffer of two buffers configuring an n+1th stage and a second shift register configuring the n+1th stage are provided in an n+3th horizontal portion and a fourth buffer of the two buffers is provided in an n+1th horizontal portion, and the nth horizontal portion is a region including pixels which are arranged along a 4n?3th gate line and a 4n?2th gate line.

Abstract: A light emitting display apparatus includes a substrate, a display portion including a plurality of pixel driving lines disposed over the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light emitting device layer including a self-emitting device disposed at the display portion, a dam disposed along an edge portion of the substrate, the dam including a metal line, an encapsulation layer including an organic encapsulation layer disposed on an encapsulation region surrounded on at least four sides by the dam, and an anti-electrostatic circuit selectively disposed in outermost pixels of the plurality of pixels, wherein the anti-electrostatic circuit is electrically coupled between a pixel driving line of the plurality of pixel driving lines, the pixel driving line being disposed in at least one of the outermost pixels and the metal line disposed in the dam.

Abstract: A light emitting display apparatus includes a display portion including a plurality of pixel driving lines disposed over a substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light emitting device layer disposed at the display portion, a dam portion including at least one dam having a metal line, a plurality of switching circuit portions disposed to overlap the at least one dam and selectively connected to the plurality of pixel driving lines, and a front pad portion including a plurality of front pads electrically coupled to the plurality of pixel driving lines and the metal line of the at least one dam, each of the plurality of switching circuit portions includes first and second switching circuits each including a gate electrode electrically coupled to the metal line of the at least one dam.

Abstract: Disclosed is a gate driving circuit comprising a plurality of stage circuits dependently connected to each other and configured to output ‘j’ output signals ('j? is an integer of 2 or more), wherein each of the plurality of stage circuits includes a logic controller for controlling a voltage of each of first and second nodes, and an output circuit unit for outputting each of ‘j’ clock signals as the ‘j’ output signal in response to the voltage of the first node, wherein the output circuit unit includes ‘j’ output buffers for outputting each of the ‘j’ clock signals as the ‘j’ output signal through an output node in response to the voltage of the first node, and a capacitor prepared between the first node and the output node of some of the ‘j’ output buffers.