Abstract: An improved bit sequential type parallel comparator capable of locating a minimum value among values of `m` bits stored in `n` registers within `m` clock cycles and the location thereof by bit-sequentially receiving those values, which includes a bit sequential type parallel comparator, which includes a minimum data detection circuit for detecting a minimum data by comparing a data of `m` bits sequentially inputted from `n` registers within `m` clock cycles; a minimum data generation circuit for generating a 1's complementary value of a minimum data using the data of `n` bits obtained by the minimum data detection circuit and an enable signal inputted from an eternally connected element; a minimum location information detection circuit for detecting a location of the minimum value among the `n` register values using the data obtained by the minimum data generation circuit and the data obtained by the minimum data detection circuit and for resetting the minimum data detection circuit upon location of the minim