Abstract: The present disclosure relates to a method for preparing a non-woven fabric which improves impregnation and release properties of a fabric softener in the non-woven fabric in order to apply the non-woven fabric to a dryer sheet (sheet-type fabric softener). When increasing porosity and specific surface area in a non-woven fabric made of two-component blended polyester long fibers, impregnation and release rate of a fabric softener are improved even when the non-woven fabric is lightened, making it possible to apply the non-woven fabric to a dryer sheet.

Abstract: An anti-icing honeycomb core composite manufactured by forming an electromagnetic wave absorption layer by using dielectric fiber, molding the electromagnetic wave absorption layer into a honeycomb core structure by using a molded part including a first base, a second base, and an inner block, hardening the honeycomb core structure, and removing the molded part. The molding step includes first stacking, on the first base including a plurality of grooves in which the inner blocks each having a hexagonal column shape are able to be seated, a plurality of the inner blocks and a plurality of the electromagnetic wave absorption layers as the honeycomb core structure so that the electromagnetic wave absorption layer is disposed between the plurality of inner blocks, and second stacking covering the inner blocks and the electromagnetic wave absorption layers stacked on the first base with the second base having the same shape as the first base.

Abstract: An apparatus for combining PCBs may include a pick-up mechanism, a gripping mechanism and a combining mechanism. The pick-up mechanism may pick-up the PCBs connected with each other by a flexible connection member. The gripping mechanism may grip a frame. The combining mechanism may press the flexible connection member using the frame to combine the PCBs with the frame. The process for combining the PCBs with the frame may be automatically performed so that a time for combining the PCBs with the frame is reduced and errors related to the combining process are decreased.

Abstract: An apparatus for combining PCBs may include a pick-up mechanism, a gripping mechanism and a combining mechanism. The pick-up mechanism may pick-up the PCBs connected with each other by a flexible connection member. The gripping mechanism may grip a frame. The combining mechanism may press the flexible connection member using the frame to combine the PCBs with the frame. The process for combining the PCBs with the frame may be automatically performed so that a time for combining the PCBs with the frame is reduced and errors related to the combining process are decreased.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract: A method of aligning a wafer includes recognizing images of the wafer accommodated on a work table and a notch of the wafer using a camera, designating at least one notch point of the notch in a recognized image, producing at least one reference line using the designated notch point in the recognized image, designating a center point of the reference line in the recognized image, producing an imaginary line having an angle with respect to the reference line from the center point of the reference line in the recognized image, producing a center line of the wafer using the imaginary line in the recognized image, and aligning the wafer using an alignment apparatus to allow the center line of the wafer and an alignment line of the work table to be matched.

Abstract: A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure.

Abstract: According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on the substrate. A sacrificial pattern electrically connected to the metal interconnection and serving as a sacrificial anode for cathodic protection against corrosion of the metal interconnection may be formed on the second area. An opening to expose the metal interconnection on the first area may be formed by patterning the insulating layer. An electronic device fabricated by a method according to an example embodiment may include a substrate, a metal interconnection, an insulating layer, and/or a sacrificial pattern.

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract: A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.