Patents by Inventor Youngshin Eum
Youngshin Eum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220293724Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventors: JUN SAITO, KEITA KATAOKA, YUSUKE YAMASHITA, YUKIHIKO WATANABE, KATSUHIRO KUTSUKI, YOUNGSHIN EUM
-
Publication number: 20220278231Abstract: A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ? (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm?2), Q>?*Ec/e.Type: ApplicationFiled: May 18, 2022Publication date: September 1, 2022Inventors: Jun SAITO, Youngshin EUM, Keita KATAOKA, Yusuke YAMASHITA, Yukihiko WATANABE, Katsuhiro KUTSUKI
-
Patent number: 11056584Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.Type: GrantFiled: November 25, 2019Date of Patent: July 6, 2021Assignee: DENSO CORPORATIONInventors: Kensuke Hata, Shinichi Hoshi, Hideo Matsuki, Youngshin Eum, Shigeki Takahashi
-
Patent number: 10714606Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.Type: GrantFiled: September 5, 2016Date of Patent: July 14, 2020Assignee: DENSO CORPORATIONInventors: Youngshin Eum, Kazuhiro Oyama, Yasushi Higuchi, Yoshinori Tsuchiya, Shinichi Hoshi
-
Patent number: 10629716Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 ?m to 5 ?m both inclusive.Type: GrantFiled: April 6, 2017Date of Patent: April 21, 2020Assignee: DENSO CORPORATIONInventors: Hiroyuki Tarumi, Kazuhiro Oyama, Youngshin Eum, Shinichi Hoshi
-
Publication number: 20200091332Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: KENSUKE HATA, SHINICHI HOSHI, HIDEO MATSUKI, YOUNGSHIN EUM, SHIGEKI TAKAHASHI
-
Publication number: 20190123187Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 ?m to 5 ?m both inclusive.Type: ApplicationFiled: April 6, 2017Publication date: April 25, 2019Inventors: Hiroyuki TARUMI, Kazuhiro OYAMA, Youngshin EUM, Shinichi HOSHI
-
Patent number: 10109727Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.Type: GrantFiled: December 8, 2015Date of Patent: October 23, 2018Assignee: DENSO CORPORATIONInventors: Kazuhiro Oyama, Yasushi Higuchi, Seigo Oosawa, Masaki Matsui, Youngshin Eum
-
Publication number: 20180248026Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.Type: ApplicationFiled: September 5, 2016Publication date: August 30, 2018Inventors: Youngshin EUM, Kazuhiro OYAMA, Yasushi HIGUCHI, Yoshinori TSUCHIYA, Shinichi HOSHI
-
Patent number: 10062747Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.Type: GrantFiled: June 14, 2016Date of Patent: August 28, 2018Assignee: DENSO CORPORATIONInventors: Youngshin Eum, Kazuhiro Oyama, Yasushi Higuchi, Shinichi Hoshi
-
Publication number: 20180130873Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.Type: ApplicationFiled: June 14, 2016Publication date: May 10, 2018Inventors: Youngshin EUM, Kazuhiro OYAMA, Yasushi HIGUCHI, Shinichi HOSHI
-
Publication number: 20170345919Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.Type: ApplicationFiled: December 8, 2015Publication date: November 30, 2017Inventors: Kazuhiro OYAMA, Yasushi HIGUCHI, Seigo OOSAWA, Masaki MATSUI, Youngshin EUM
-
Publication number: 20130248878Abstract: Disclosed is a nitride semiconductor device and a method for manufacturing the same and the method for manufacturing the nitride semiconductor device comprising: growing a buffer layer including a first semiconductor on a substrate; growing a first barrier layer including a second semiconductor different from the first semiconductor; forming an oxide film layer on a portion where a recess is to be formed; growing a second barrier layer including the second semiconductor; forming a recess by removing the oxide film layer; and forming a gate electrode on the recess.Type: ApplicationFiled: November 15, 2011Publication date: September 26, 2013Applicant: LG Electronic Inc.Inventors: Taehoon Jang, Youngshin Eum
-
Publication number: 20130119397Abstract: Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode.Type: ApplicationFiled: November 14, 2012Publication date: May 16, 2013Inventors: Youngshin Eum, Taehoon Jang