Abstract: The present disclosure discloses systems and methods of calculating a near-maximum likelihood detection (MLD) performance capability signal to interference plus noise ratio (SINR) according to instructions stored in non-transitory computer readable memory that when executed by a processor of a multiple-input, multiple output orthogonal frequency-division multiplexing (MIMO-OFDM) wireless communications receiver device cause the processor to perform operations including the processor acquiring Hi and noise variance ?n2 for each subcarrier of a set of subcarriers between a MIMO-OFDM wireless communications transmitter device and the wireless communications receiver device, computing an average received bit mutual information rate (RBIR) over all subcarriers, converting the average RBIR to an effective SINR; and selecting a modulation coding scheme (MCS).

Abstract: Systems, methods and apparatus related to pre-wetting an edge portion of a bonded wafer prior to wetting a flat, horizontal portion of the bonded wafer. The apparatus includes a frame having nozzles directed such that couplant discharged from these nozzles wet the edge of the wafer. The edge nozzles have couplant flow vectors that interface to dampen the trajectory of fluid to reduce splash and pre-wet the edges of the bonded wafer.

Abstract: A coupler and a chuck are described. The chuck is configured to secure an article while the wafer is undergoing an inspection process. The chuck has a plurality of vacuum areas. Some vacuum areas hold the wafer in place while other vacuum areas suction couplant from the edge surface of the wafer. The coupler is used to inspect a surface and subsurface of the wafer for defects and includes a sensing device, which may be a transducer. One or more couplant inlet couplings are disposed on a second portion of the coupler, the couplant inlet couplings provide a couplant to a portion of the wafer inspected by the sensing device. A plurality of vacuum inlet couplings is disposed on a third portion of the coupler. At least one of the vacuum inlet couplings provide suction through a recessed portion of a lower surface of the coupler to remove couplant that is outside the portion of the wafer that is being inspected by the sensing device.

Abstract: A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract: A tape wiring substrate includes a base film having at least one recess in a first surface of the base film and a chip-mounting region on which a semiconductor chip is included on a second surface of the base film. A wiring pattern is formed on the second surface of the base film and is extended to an edge of the chip-mounting region. A protection film covers the wiring pattern.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A solid-state imaging apparatus and method for manufacturing the imaging apparatus. A solid-state imaging apparatus with reduced thickness and/or mounting area by forming an aperture in a board and placing a solid-state semiconductor imaging chip, an image processing semiconductor chip, and/or a combination imaging/processing chip within the aperture.

Abstract: An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract: An image pickup device and a manufacturing method thereof. A digital signal processing (DSP) chip is attached on a first surface of a substrate. A CMOS image sensor (CIS) chip is attached on an active surface of the DSP chip. The DSP chip and the CIS chip may be electrically connected to the substrate by wire bonding. A housing kit having a lens configured to transmit an image to the DSP chip may be mounted on the substrate. An inner space between the housing kit and the substrate is not molded, thereby simplifying a manufacturing process and providing a thinner and/or lighter image pickup device.

Abstract: Disclosed are a repairable multi-chip package and a high-density memory card having the multi-chip package. The package includes a circuit substrate having bonding tips on a first surface and external contact pads on a second surface opposite to the first surface. The bonding tips and the external contact pads are electrically connected to each other. The package also includes at least two memory chips each mounted on the first surface and having chip pads thereon. The package includes electrically connecting members coupling each bonding tip to each chip pad, and an encapsulation layer covering the chips and the electrically connecting members. Particularly, the encapsulation layer is divided into two or more parts, and the bonding tips are partially embedded in and partially exposed out of the divided encapsulation layer. Accordingly, the exposed bonding tips can be selectively cut or re-connected for repairing the multi-chip package.

Abstract: A high-density memory card comprises a base card and two packages fixedly mounted within the base card. The two packages are attached to the base card and face each other. In one embodiment, a first package comprises a first substrate and at least one memory chip, and a second package comprises a second substrate and at least one memory chip. A first surface of the first substrate has external connection pads formed thereon and is exposed from the memory card. A second surface of the first substrate has first connection pads formed thereon. The memory chips are mounted on the second surface and electrically connected to each other. A third surface of the second substrate is exposed from the memory card, and a fourth surface of the second substrate has second connection pads formed thereon. The memory chips are mounted on the fourth surface and electrically connected to each other.

Abstract: The present invention provides a memory card having a reduced size as much as that of the package. The memory card includes electrical contact pads disposed in a single row on one end of the memory card. The memory card further comprises a card base and a semiconductor package. The card base has a first surface and a second surface, the first surface having a cavity formed thereon. The semiconductor package comprises a substrate, memory chips, and a molding resin layer, and is mounted on the cavity so that the external contact pads are exposed. Circuit wirings are formed on an inner surface of the substrate and electrically connected to the external contact pads that are formed on an outer surface of the substrate.

Abstract: Disclosed are a repairable multi-chip package and a high-density memory card having the multi-chip package. The package includes a circuit substrate having bonding tips on a first surface and external contact pads on a second surface opposite to the first surface. The bonding tips and the external contact pads are electrically connected to each other. The package also includes at least two memory chips each mounted on the first surface and having chip pads thereon. The package includes electrically connecting members coupling each bonding tip to each chip pad, and an encapsulation layer covering the chips and the electrically connecting members. Particularly, the encapsulation layer is divided into two or more parts, and the bonding tips are partially embedded in and partially exposed out of the divided encapsulation layer. Accordingly, the exposed bonding tips can be selectively cut or re-connected for repairing the multi-chip package.