Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

Abstract: A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Abstract: An apparatus and method for encrypting/decrypting information, and the encrypting/decrypting system using the same, and a computer readable recording medium storing programs for realizing the above are disclosed. A method for encrypting information on a basic element-by-basic element basis, includes the steps of: a) receiving information to be encrypted; b) generating random number maps; c) decomposing the information into a plurality of basic elements which are classified into multiple channels; d) encrypting the basic elements and generating encrypted information; and e) outputting the encrypted information.

Abstract: The present invention relates to vinyl-phenyl monomers and polymers prepared therefrom. More particularly, the present invention is to provide the vinyl-phenyl monomers expressed by formula (1) which are capable of various polymerization such as radical polymerization, cation polymerization, anion polymerization and metallocene catalyzed polymerization due to resonance effect of phenyl group and changing characteristics variously and thus, suitable in the synthesis of general-purpose polymers which can be used in photo-functional materials by forming a complex with a metal component having an optical characteristic.

Abstract: The present invention relates to vinyl-phenyl monomers and polymers prepared therefrom. More particularly, the present invention is to provide the vinyl-phenyl monomers expressed by formula (1) which are capable of various polymerization such as radical polymerization, cation polymerization, anion polymerization and metallocene catalyzed polymerization due to resonance effect of phenyl group and changing characteristics variously and thus, suitable in the synthesis of general-purpose polymers which can be used in photo-functional materials by forming a complex with a metal component having an optical characteristic.

Abstract: The present invention relates to vinyl-phenyl monomers and polymers prepared therefrom.

Abstract: The present invention relates to vinyl-phenyl monomers and polymers prepared therefrom. More particularly, the present invention is to provide the vinyl-phenyl monomers expressed by formula (1) which are capable of various polymerization such as radical polymerization, cation polymerization, anion polymerization and metallocene catalyzed polymerization due to resonance effect of phenyl group and changing characteristics variously and thus, suitable in the synthesis of general-purpose polymers which can be used in photo-functional materials by forming a complex with a metal component having an optical characteristic.