Patents by Inventor Younjo Mun

Younjo Mun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package frame and method of manufacturing semiconductor package using the same
    Patent number: 10147616
    Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soojae Park, Geunwoo Kim, Keunho Jang, Younjo Mun
  • PACKAGE FRAME AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME
    Publication number: 20160120032
    Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.
    Type: Application
    Filed: October 26, 2015
    Publication date: April 28, 2016
    Inventors: SOOJAE PARK, GEUNWOO KIM, KEUNHO JANG, YOUNJO MUN
  • Semiconductor package
    Publication number: 20100084758
    Abstract: Provided is a semiconductor package including a mark pattern and a method of manufacturing the same. The semiconductor package may include at least one semiconductor chip including a circuit region, a protection layer covering the circuit region, a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and a mark pattern at the top surface of the molding portion. A method of fabricating the semiconductor package may include providing at least one semiconductor chip including a circuit region, forming a protection layer covering the circuit region, forming a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and forming a mark pattern at the top surface of the molding portion using a laser.
    Type: Application
    Filed: September 10, 2009
    Publication date: April 8, 2010
    Inventor: Younjo Mun