Abstract: A sensor assembly for sensing an analyte in a sample matrix comprises an electrode assembly comprising a set of at least one test electrode and may also comprise one or more control electrodes and/or an applicator assembly. The electrode assembly is configured or configurable to define one or more active test electrodes of the set of one or more test electrodes, and at least one of the electrode assembly and the applicator assembly is or are configured or configurable to adjust a quantity of the analyte provided to the active electrode(s), per unit time, for said interaction based at least in part on an analyte characteristic. Alternatively or additionally, the electrode assembly is configured and arranged in a flow path such that the amounts of sample matrix provided to the test electrode(s) and control electrode(s) of the electrode assembly are substantially equal.

Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.

Abstract: The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.

Abstract: The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.

Abstract: The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is

Abstract: The invention provides an implantable multi-electrode device (300) and related methods and apparatuses. In one embodiment, the invention includes an implantable device (300) comprising: an assembly block (320); and a plurality of leads (340 . . . 348) radiating from the assembly block (320), each of the plurality of leads (340 . . . 348) containing at least one electrode (342A), such that the electrodes are distributed within a three-dimensional space, wherein the assembly block (320) includes a barb (350) for anchoring the assembly block (320) within implanted tissue.

Abstract: A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.

Abstract: A method is disclosed using a feedback loop for focused ultrasound application. The method includes the steps of determining a location of a target side within a body using ultrasound waves, applying focused ultrasound waves to the target site, determining a new location of the target site using further ultrasound waves, and adjusting the focused ultrasound waves in response to the new location of the target site.

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Abstract: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is

Abstract: A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed.