Patents by Inventor Youssef Karmous

Youssef Karmous has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538511
    Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: December 27, 2022
    Assignee: Ciena Corporation
    Inventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
  • Publication number: 20220254394
    Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Applicant: Ciena Corporation
    Inventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski