Abstract: A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of a row address in a previous cycle and a row address in a current cycle, and a row address decoder that decodes the row address, and outputs a word line select signal to select one of word lines connected to a part of the plurality of memory cells based on the decoded row address, and prevents the output of the word line select signal when the control signal outputted from the comparator is inputted to the row address decoder.