Patents by Inventor Yousuke Nakamura

Yousuke Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180067766
    Abstract: A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 8, 2018
    Inventors: Junichi SATO, Koji ADACHI, Yousuke NAKAMURA
  • Patent number: 9896703
    Abstract: An object of the present invention is to provide a method in which a fat and/or oil is produced by a transesterification reaction using a lipase. Specifically, the present invention relates to a method for producing a transesterified fat and/or oil, comprising: (1) a low-temperature clay treatment step of bringing a fat and/or oil and a clay into contact with each other at 30 to 80° C. to obtain a reaction substrate; and (2) a step of subjecting the reaction substrate to a transesterification reaction in the presence of a lipase-containing composition.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 20, 2018
    Assignee: The Nisshin OilliO Group, Ltd.
    Inventors: Yousuke Nakamura, Yuto Nakazawa, Yuko Toyama, Yoshie Yamauchi, Hidetaka Uehara
  • Publication number: 20180012552
    Abstract: The present invention provides a data processing device connected with an intermission driving. The data processing device achieves a satisfactory power saving while ensuring a high level of display quality of the display device. Upon detection of non-data update in a frame buffer, the host calculates a next refreshing timing based on driving information obtained from a liquid crystal display device (LCD), sets a timer for a timeout after a length of time representing the calculated result, and then the host and the LCD shift to Intermission State 1. Thereafter, when the timer times out to bring the host back to Normal State and a data update at the frame buffer is detected, data for refreshing an display image in the LCD is transferred from the host to the LCD. If the amount of time representing the calculated result is longer than a predetermined baseline, a shift is made to Intermission State 2 which provides greater power saving than Intermission State 1.
    Type: Application
    Filed: November 27, 2015
    Publication date: January 11, 2018
    Inventors: TERUHISA MASUI, YOUSUKE NAKAMURA, NORIYUKI TANAKA, TATSUHIKO SUYAMA
  • Patent number: 9841996
    Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junichi Sato, Koji Adachi, Yousuke Nakamura
  • Publication number: 20170148370
    Abstract: There is provided a display device that is capable of suppressing occurrence of brightness drop which is caused by refresh of a display image during pause driving. In a normal driving mode, input image data (SsD0) according to a continuous tone method is supplied to a source driver (310) through a data selector (230) as an image signal (SsD) for driver. On the other hand, in a low-frequency driving mode in which pause driving is performed, the input image data (SsD0) is converted into dithered input image data (SsD1) by a dithering processing circuit (220), and is supplied to the source driver (310) through the data selector (230) as the image signal (SsD) for driver. A gradation of the dithered input image data (SsD1) is represented in a pseudo manner by an area coverage modulation method by using two values of a maximum value and a minimum value that can be taken as the gradation value of the input image data (SsD0).
    Type: Application
    Filed: June 18, 2015
    Publication date: May 25, 2017
    Inventors: Yousuke NAKAMURA, Tatsuhiko SUYAMA, Teruhisa MASUI, Kentaroh UEMURA
  • Patent number: 9654764
    Abstract: A stereoscopic image processing device including a depth map generation unit and a depth map correction unit. The depth map generation unit uses a first viewpoint image and a second viewpoint image to acquire depth values in units of blocks constituted of a plurality of pixels and generate a depth map. The depth map correction unit performs a judgment in the depth map as to whether or not a boundary region is included in a block of interest based on depth values of blocks surrounding the block of value, which is a block to be processed, and, if a boundary region is judged to be included in the block of interest, corrects the depth values in units of correction regions, which are units which are smaller than blocks, in the block of interest.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 16, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Jun Hamachi, Teruhisa Masui, Yousuke Nakamura
  • Publication number: 20170109202
    Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Junichi SATO, Koji ADACHI, Yousuke NAKAMURA
  • Patent number: 9569261
    Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junichi Sato, Koji Adachi, Yousuke Nakamura
  • Patent number: 9460317
    Abstract: A non-transitory computer-readable medium for recording a program allowing a computer to execute: determining whether first identification information of the computer matches with second identification information stored in the computer-readable medium connected to the computer; executing a process stored in the computer-readable medium upon the determining that the first identification information and the second identification information do not match; selecting a communication unit from one or a plurality of communication units included in the computer; and transmitting third information regarding the execution of the process using the selected communication unit.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 4, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kazuaki Nimura, Kouichi Yasaki, Yousuke Nakamura, Zhaogong Guo, Isamu Yamada
  • Publication number: 20160132689
    Abstract: A communication control device configured to access an information processing apparatus in which data is stored. The device and method acquires an operational condition of an information processing apparatus, and notifies the information processing apparatus of a security command for causing the information processing apparatus to execute a security process on the data in an event that an operational condition is activated and, in an event that the operational condition is a standby mode, a hibernate mode, or a shutdown mode, notifies the information processing apparatus of an activation command for activating the information processing apparatus, and notifies of a security command for causing the information processing apparatus to execute a security process on the data.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Kazuaki NIMURA, Yousuke NAKAMURA, Kouichi YASAKI, Fumio HONDA
  • Publication number: 20160053876
    Abstract: A power transmission device includes a pulley constituting a driving-side rotor, an inner hub, a washer and a limiter which constitute a driven-side rotor, and a plate configured as a linking elastic member that connects the driving-side rotor and the driven-side rotor. A flat spring that elastically deforms in a direction along a rotation shaft is adopted as the plate. A distance in an axial direction between a pulley-side attachment portion of the plate which is attached to the pulley and a hub-side attachment portion of the plate which is attached to the inner hub is adjusted to fall within a predetermined standard range by interposing a shim as an adjustment member between the plate and the pulley.
    Type: Application
    Filed: March 28, 2014
    Publication date: February 25, 2016
    Inventors: Yousuke NAKAMURA, Manabu SAIKI, Kiyomi OKUDA
  • Patent number: 9262650
    Abstract: A communication control device configured to access an information processing apparatus in which data is stored. The device and method acquires an operational condition of an information processing apparatus, and notifies the information processing apparatus of a security command for causing the information processing apparatus to execute a security process on the data in an event that an operational condition is activated and, in an event that the operational condition is a standby mode, a hibernate mode, or a shutdown mode, notifies the information processing apparatus of an activation command for activating the information processing apparatus, and notifies of a security command for causing the information processing apparatus to execute a security process on the data.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kazuaki Nimura, Yousuke Nakamura, Kouichi Yasaki, Fumio Honda
  • Publication number: 20150299747
    Abstract: An object of the present invention is to provide a method in which a fat and/or oil is produced by a transesterification reaction using a lipase. Specifically, the present invention relates to a method for producing a transesterified fat and/or oil, comprising: (1) a low-temperature clay treatment step of bringing a fat and/or oil and a clay into contact with each other at 30 to 80° C. to obtain a reaction substrate; and (2) a step of subjecting the reaction substrate to a transesterification reaction in the presence of a lipase-containing composition.
    Type: Application
    Filed: March 7, 2013
    Publication date: October 22, 2015
    Inventors: Yousuke NAKAMURA, Yuto NAKAZAWA, Yuko TOYAMA, Yoshie YAMAUCHI, Hidetaka UEHARA
  • Patent number: 9143556
    Abstract: An application providing system has a communication terminal, a Web server that manages resources of Web applications, and a push server that manages storage location addresses of resources. The push server has an address managing unit that manages a terminal ID, a storage location address, and providing timing in a manner associated with one another. The push server further has a timing monitoring unit that monitors the providing timing. The push server further has a push transmitting unit that transmits a storage location address of a resource of a Web application associated with providing timing to a communication terminal associated with the providing timing upon detection of the providing timing to cache the resource of the Web application corresponding to the providing timing in the communication terminal.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: September 22, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hidenobu Ito, Kazuaki Nimura, Yousuke Nakamura, Kouichi Yasaki, Zhaogong Guo
  • Publication number: 20150222879
    Abstract: A stereoscopic image processing device is realized whereby a parallax map (depth map) can be acquired with a small amount of computation and high-precision stereoscopic image processing can be executed. A stereoscopic image processing device including a depth map generation unit and a depth map correction unit. The depth map generation unit uses a first viewpoint image and a second viewpoint image to acquire depth values in units of blocks constituted of a plurality of pixels and generate a depth map. The depth map correction unit performs a judgment in the depth map as to whether or not a boundary region is included in a block of interest based on depth values of blocks surrounding the block of value, which is a block to be processed, and, if a boundary region is judged to be included in the block of interest, corrects the depth values in units of correction regions, which are units which are smaller than blocks, in the block of interest.
    Type: Application
    Filed: August 12, 2013
    Publication date: August 6, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Jun Hamachi, Teruhisa Masui, Yousuke Nakamura
  • Publication number: 20150019616
    Abstract: An application providing system has a communication terminal, a Web server that manages resources of Web applications, and a push server that manages storage location addresses of resources. The push server has an address managing unit that manages a terminal ID, a storage location address, and providing timing in a manner associated with one another. The push server further has a timing monitoring unit that monitors the providing timing. The push server further has a push transmitting unit that transmits a storage location address of a resource of a Web application associated with providing timing to a communication terminal associated with the providing timing upon detection of the providing timing to cache the resource of the Web application corresponding to the providing timing in the communication terminal.
    Type: Application
    Filed: October 1, 2014
    Publication date: January 15, 2015
    Inventors: Hidenobu ITO, Kazuaki NIMURA, Yousuke NAKAMURA, Kouichi YASAKI, Zhaogong GUO
  • Patent number: 8924738
    Abstract: An information processing device and method include storing encrypted content, storing a key for decrypting the encrypted content stored, decrypting the encrypted content stored using the key, storing a deletion table storing information indicating whether or not the key stored is to be deleted when a transition from an operating state to one of other states is made, the information corresponding to the other states, and checking the information in the deletion table corresponding to the one of the other states and deleting the key when the information indicates that the key is to be deleted.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Nimura, Yousuke Nakamura, Fumio Honda, Isamu Yamada
  • Patent number: 8880673
    Abstract: An application providing system has a communication terminal, a Web server that manages resources of Web applications, and a push server that manages storage location addresses of resources. The push server has an address managing unit that manages a terminal ID, a storage location address, and providing timing in a manner associated with one another. The push server further has a timing monitoring unit that monitors the providing timing. The push server further has a push transmitting unit that transmits a storage location address of a resource of a Web application associated with providing timing to a communication terminal associated with the providing timing upon detection of the providing timing to cache the resource of the Web application corresponding to the providing timing in the communication terminal.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: November 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Hidenobu Ito, Kazuaki Nimura, Yousuke Nakamura, Kouichi Yasaki, Zhaogong Guo
  • Patent number: 8856554
    Abstract: An information terminal includes: a storage unit to store information; a data encryption unit to encrypt the information and decrypt the encrypted information using an encryption key; a pre-deletion unit to delete the encryption key; a signal detection unit to detect an interruption signal; a pre-deletion setting unit to instruct the pre-deletion unit to delete the encryption key in response to the detection of the interruption signal; and a deletion stop unit to stop deletion of the encryption key by the pre-deletion unit.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Limited
    Inventors: Kouichi Yasaki, Hidenobu Ito, Yousuke Nakamura, Kazuaki Nimura, Zhaogong Guo
  • Patent number: 8812829
    Abstract: An information processing apparatus includes, a processer, a non-volatile memory to store a plurality of programs, a volatile memory to store at least one program executed by the processor and data accessed by the program, an acceptance unit to accept context information when power supplied to the processor is resumed from a state in which power supplied to the processor is interrupted while a power supplied to the volatile memory is maintained, a selection unit to select one program from the plurality of programs stored in the non-volatile memory based on context information accepted by the acceptance unit, and a program determination unit to determine whether the one program selected by the selection unit is stored in the volatile memory. When the processor determines the one program selected by the program determination unit is stored in the volatile memory, the processor starts the one program stored in the volatile memory.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Nimura, Zhaogong Guo, Kouichi Yasaki, Yousuke Nakamura