Abstract: Disclosed is an organic light-emitting diode display device including: a display panel in which pixels adjacent to each other are paired and arranged to share a single data line in pixel areas defined by gate and data lines; a gate driver configured to drive the plurality of gate lines; a data driver configured to output a data voltage to data voltage output channels on the basis of an arrangement of pixels; a data switcher configured to alternately select a data line and to electrically connect the data line with the data voltage output channel of the data driver; and a timing controller configured to control the data switcher and the gate and data drivers, thereby making it possible to drive a data driving circuit at high driving frequency and to reduce a deterioration of image quality and image distortion even in a simplified structure of the data driving circuit.

Abstract: Disclosed is an organic light-emitting diode display device including: a display panel in which pixels adjacent to each other are paired and arranged to share a single data line in pixel areas defined by gate and data lines; a gate driver configured to drive the plurality of gate lines; a data driver configured to output a data voltage to data voltage output channels on the basis of an arrangement of pixels; a data switcher configured to alternately select a data line and to electrically connect the data line with the data voltage output channel of the data driver; and a timing controller configured to control the data switcher and the gate and data drivers, thereby making it possible to drive a data driving circuit at high driving frequency and to reduce a deterioration of image quality and image distortion even in a simplified structure of the data driving circuit.

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

Abstract: A liquid-crystal display device and a driving method thereof are disclosed. The driving method of the liquid-crystal display device comprises: generating first and second power supply voltages; generating gamma-compensated voltages based on the first and second power supply voltages; converting data of an input image to the gamma-compensated voltages to output data voltages; distributing, by a multiplexer, the data voltages output from the data driver to a plurality of data lines; and varying at least one of the first and second power supply voltages at a given time interval.

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

Abstract: A liquid-crystal display device and a driving method thereof are disclosed. The driving method of the liquid-crystal display device comprises: generating first and second power supply voltages; generating gamma-compensated voltages based on the first and second power supply voltages; converting data of an input image to the gamma-compensated voltages to output data voltages; distributing, by a multiplexer, the data voltages output from the data driver to a plurality of data lines; and varying at least one of the first and second power supply voltages at a given time interval.

Abstract: A timing controller capable of adjusting luminance of a maximum gradation according to an amount of white of image data to thus enhance picture quality and reduce power consumption of a liquid crystal display device, a liquid crystal display device having the same, and a driving method thereof are provided. The timing controller includes: a gamma adjusting unit for receiving image data and a plurality of driving signals input from the outside, generating a gate control signal and a data control signal according to the plurality of driving signals, adjusting luminance according to an amount of white in the image data, and generating a corresponding gamma control signal.

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

Abstract: A display device for low speed drive includes a display panel including gate lines, data lines, and pixels respectively formed at crossings of the gate lines and the data lines, a source driver supplying data voltages to the data lines, a gate driver supplying a gate pulse to the gate lines, and a timing controller which time-divides one frame into n sub-frames, where n is a positive integer equal to or greater than 2, groups the gate lines into n gate groups, controls an operation of the gate driver in each of the n sub-frames to complete a scan operation of a corresponding gate group during a scan period of each of the n sub-frames, generates a buffer operation control signal, and cuts off a driving power source applied to buffers of the source driver during a skip period excluding the scan period from each of the n sub-frames.

Abstract: A liquid crystal display includes according to an embodiment a display panel provided with a plurality of data lines, a plurality of gate lines intersecting the data lines, liquid crystal cells arranged in a matrix, and TFTs disposed at the intersections of the data lines and the gate lines; source drive ICs configured to supply data voltages to the data lines, wherein polarities of data voltages are reversed by a column inversion scheme; and a gate driver configured to sequentially supply gate pulses for the gate lines, wherein polarities of the data voltages charged in the liquid crystal cells in the display panel are reversed in dot unit.

Abstract: A liquid crystal display includes according to an embodiment a display panel provided with a plurality of data lines, a plurality of gate lines intersecting the data lines, liquid crystal cells arranged in a matrix, and TFTs disposed at the intersections of the data lines and the gate lines; source drive ICs configured to supply data voltages to the data lines, wherein polarities of data voltages are reversed by a column inversion scheme; and a gate driver configured to sequentially supply gate pulses for the gate lines, wherein polarities of the data voltages charged in the liquid crystal cells in the display panel are reversed in dot unit.