Abstract: A reiterative learning procedure with training and test processes for a binary supervised neural network includes at least an error signal generator for weighting factor updating in the training process, which generates an error signal that is perturbed in polarity and amplitude in the difference derived by subtracting an output unit signal from corresponding binary teacher signal and then generates the difference as an error signal after a maximum absolute value of differences among erroneous binary output signals has become smaller than a threshold once. A training signal memory stores a set of training signals and adds test signals providing erroneous binary output signals that are transferred from a test signal memory in the test process to the set of training input signals as incremental training input signals.

Abstract: In a parallel multi-value neural network having a main neural network 16 and a sub neural network 18 coupled with the main neural network 16 in parallel for an input signal, the main neural network 16 is trained with a training input signal by using a main multi-value teacher signal, and the sub neural network is successively trained with the training input signal by using multi-value errors between a multi-value output signal of the main neural network 16 derived through a multi-value threshold means 17 and the main multi-value teacher signal, so as to compensate the multi-value errors involved in the multi-value output signal of the main neural network 16 by the multi-value output signal of the sub neural network 18 derived through a multi-value threshold means 19. A desired multi-value output signal of the parallel multi-value neural network 15 is obtained by adding in modulo the multi-value output signals of both the neural networks through a multi-value modulo adder 20.

Abstract: A learning method supervised by a binary teacher signal for a binary neural network comprises at least an error signal generator 10 for weighting factor updating, which generates an error signal for weighting factor updating having an opposite polarity to that of a difference signal between an output unit signal of the binary neural network and the binary teacher signal on an output unit whereat a binary output unit signal coincides with the binary teacher signal, and an amplitude which decreases by increase of distance from the binary teacher signal, when an absolute value of the difference signal is smaller than a threshold, generates an error signal which has the same polarity as that of the difference signal and an amplitude smaller than that of the difference signal, when the absolute value of the difference signal is larger than the threshold, or generates an error signal which has an amplitude equal to or smaller than that of the difference signal on an output unit providing a wrong binary output unit

Abstract: In an echo canceller having PCM interfaces used in a PCM telephone circuit, an echo estimator (6) is coupled with a receive path through a linear code converter (13) for obtaining a linear receive input signal, and a first subtractor (7) is inserted after a linear code converter (13) in a transmit path for cancelling an echo component in a linear transmit input signal and for transmitting a first residual echo to the far-end talker. A non-linear quantization processor (24) is inserted between the first subtracter (7) and the echo estimator (6), and produces a new echo estimate containing quantization noise, based on an echo estimate which is derived from the echo estimator (6). The filter coefficients in the echo estimator (6) are updated by using the second residual echo obtained by the second subtracter (23) separately prepared from the first subtracter (7).

Abstract: In an echo canceller used in a four-wire digital telephone circuit, a main echo estimator (21) and a sub echo estimator (22) are coupled with a receive path for measuring a receive signal, and subtracters (25, 26) are inserted in a transmit path for cancelling an echo component in a transmit signal. Filter coefficients in said estimators (21, 22) are adaptively controlled by a convergence control processor (24). The main echo estimator has a small step gain for updating filter coefficients so that the response to an echo is slow, while the sub echo estimator (22) has a large step gain and quick response for an echo. An register accumulator (23) is provided so that the filter coefficients by the sub echo estimator (22) are selectively accumulated on the related filter coefficients in the main echo estimator (21) according to operation modes, ordinary mode, accumulating mode, and reset mode.