Patents by Inventor Youvedeep Singh
Youvedeep Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768533Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: August 2, 2022Date of Patent: September 26, 2023Assignee: Tahoe Research, Ltd.Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20230004209Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: August 2, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 11422615Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: January 13, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10768680Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: GrantFiled: August 15, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Publication number: 20200272219Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: January 13, 2020Publication date: August 27, 2020Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10564705Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: May 18, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20180364792Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: May 18, 2018Publication date: December 20, 2018Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10007323Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: December 23, 2013Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20180059766Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: ApplicationFiled: August 15, 2017Publication date: March 1, 2018Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Patent number: 9733689Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: GrantFiled: June 27, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Publication number: 20160378160Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: ApplicationFiled: June 27, 2015Publication date: December 29, 2016Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Publication number: 20140181560Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: December 23, 2013Publication date: June 26, 2014Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor