Patents by Inventor Youvedeep Singh

Youvedeep Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11768533
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: September 26, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Publication number: 20230004209
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: August 2, 2022
    Publication date: January 5, 2023
    Applicant: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Patent number: 11422615
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Patent number: 10768680
    Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
  • Publication number: 20200272219
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: January 13, 2020
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Patent number: 10564705
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Publication number: 20180364792
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: May 18, 2018
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Patent number: 10007323
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
  • Publication number: 20180059766
    Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.
    Type: Application
    Filed: August 15, 2017
    Publication date: March 1, 2018
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
  • Patent number: 9733689
    Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
  • Publication number: 20160378160
    Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.
    Type: Application
    Filed: June 27, 2015
    Publication date: December 29, 2016
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
  • Publication number: 20140181560
    Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 26, 2014
    Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor