Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is substantially octagonal and arranged in rows and columns. If desired, square or rectangular metal fill be tiled with the substantially octagonal metal fill. Metal layers may also contain halved or quartered octagonal metal fill. Substrate in the transition zone may have octagonal substrate regions separated by shallow trench isolation regions. A polysilicon layer above the substrate may have square regions of polysilicon fill directly above the shallow trench regions in the substrate. Such arrangements may provide more uniform densities in transition zones with certain geometries.

Abstract: A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.

Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.

Abstract: A pair of SCR devices connected in antiparallel between first and second nodes. Each SCR device comprises an NPN and a PNP bipolar transistor. Reverse-biased Zener diodes are used for triggering the NPN bipolar transistor in each SCR device when it breaks down in an ESD event. Advantageously, additional Zener diodes are provided for pre-charging the PNP transistor of each SCR device at the same time, thereby reducing the delay time for turning on the PNP bipolar transistor. In addition, the breakdown current of the Zener diodes is preferably maximized by reducing the P-well and N-well resistance of the SCRs. This is achieved by connecting external resistances between the base of each bipolar transistor and the node to which the emitter of the transistor is connected.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided with adjustable configuration random-access-memory cell power supply circuitry. The adjustable configuration random-access-memory cell power supply circuitry powers configuration random-access-memory cells on an integrated circuit. During operation of the integrated circuit, the configuration random-access-memory cells provide static output signals that turn on and off associated pass transistors. The adjustable power supply circuitry can be configured to produce different power supply voltages on different portions of an integrated circuit. The different power supply voltages accommodate circuit design constraints while minimizing power consumption due to pass transistor leakage.

Abstract: A first high resolution pattern is defined in a first layer of photoresist on a work surface and portions of the first layer are removed to expose the pattern on the work surface. The exposed portions of the work surface and the remaining portions of the first layer are then covered by a second layer of photoresist. A second lower resolution pattern is then defined in the second layer and portions of the second layer are removed to expose on the work surface a third pattern that is a subset of the first pattern. Standard (non-custom) masks may be used to define the first pattern while custom but lower resolution masks are used to define the second pattern.

Abstract: The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits the terminal of the integrated circuit, the PN junction between the emitter and the base becomes forward biased. The forward biasing of the emitter-base PN junction in turn causes carriers to be injected into the collector-base junction, triggering the bipolar ESD device to turn on to discharge the ESD pulse. The trigger voltage of the bipolar ESD device is a fraction of a breakdown voltage of the collector-base PN junction and can be modified by adjusting a base length of the bipolar ESD device, a junction depth of the collector, or a dopant concentration in the base.

Abstract: The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.

Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.

Abstract: The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.

Abstract: The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

Abstract: The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.

Abstract: A method for forming a uniformly planarized structured in a semiconductor wafer forms metal structures on a substrate layer with spaces between the structures. The top surfaces of the metal structures lie within a common plane. Dielectric material is deposited on the layer, the metal structures and in the spaces. The dielectric layer is first etched so that the dielectric material in the spaces is below the common plane. Additional dielectric material is then deposited on the layer, the metal structures and in the spaces. The dielectric layer is then subjected to a second etching. Further deposition and etching steps are performed until the top of the dielectric layer and the top surfaces of the metal structures have a common, substantially uniform planarization.

Abstract: A method of performing ultra-shallow junctions in a semiconductor wafer uses a silicon layer to achieve ultra-low silicon consumption during a salicide formation process. A refractory metal layer, such as a cobalt layer, is deposited over the gate and source/drain junctions of the semiconductor device. After a rapid thermal annealing is performed to form the high-ohmic phase of the salicide, a silicon layer is deposited at a low temperature over the semiconductor device. The silicon layer provides a source of silicon for consumption during a second thermal annealing step, reducing the amount of silicon of the source/drain junctions that is consumed. The second thermal annealing step is performed in a nitrogen and oxygen atmosphere so at the silicon layer is transformed into a silicon oxynitride bottom anti-reflective coating layer.

Abstract: A method and arrangement for forming a local interconnect without etching completely through a junction and causing device shorts introduces an additional ion implantation step following the etching of the local interconnect opening into the substrate. The additional ion implantation step into the active region ensures that the depth of the junction is below the depth reached by the local interconnect opening and the substrate.

Abstract: A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased density in comparison to conventionally deposited (e.g., plasma enhanced chemical vapor deposition (PECVD) etch stop layers. A low pressure chemical vapor deposition (LPCVD) process is used to deposit LPCVD SiN, using a high temperature in the deposition chamber. The increased temperature during deposition creates a highly dense, thermal SiN etch stop layer that is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.

Abstract: A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge introduces additional nitrogen by ion implantation into a nitrogen-containing etch stop layer (e.g., SiON) that has already been deposited, by plasma enhanced chemical vapor deposition (PECVD), for example. The enriched nitrogen etch stop layer is harder to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.