Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract: A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: A method for controlling a peak current is provided. The method first uses a plurality of registers to encode a plurality of states of a circuit and generates an original state code. Then, the original state code is re-encoded to reduce the difference between the sum of charging current of the charged registers and the sum of discharging current of the discharged registers while the registers are switched among the charging/discharging states. Finally, a standard technology library is read and logic circuit synthesis is performed for the re-encoded state codes.

Abstract: A method for controlling a peak current is provided. The method first uses a plurality of registers to encode a plurality of states of a circuit and generates an original state code. Then, the original state code is re-encoded to reduce the difference between the sum of charging current of the charged registers and the sum of discharging current of the discharged registers while the registers are switched among the charging/discharging states. Finally, a standard technology library is read and logic circuit synthesis is performed for the re-encoded state codes.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.

Abstract: We propose an opposite-phase scheme for peak current reduction. The basic idea is to divide the clock buffers at each level of the clock tree into two sets: one half of the clock buffers operate at the same phase as the clock source, and the other half of the clock buffers operate at the opposite phase to the clock source. Consequently, our approach can effectively reduce the peak current of the clock tree. The method enables the opposite-phase scheme to combine with the electronic design automation (EDA) tools that are commonly used in modern industries.