Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling.

Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).

Abstract: A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling.

Abstract: A method (100) of determining a doping type and a doping concentration of a semiconductor material (101) includes the steps of moving carriers (103) in the material, wherein a number of carriers is a function of the doping concentration of the material (101) and a type of carriers is a function of the doping type of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).

Abstract: A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, each of the mesas comprising at least a first insulator layer and a second different insulated layer thereover, forming a trench between the mesas into the semiconductor substrate, removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges, forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer, and filling the trench with an insulator material.

Abstract: A quadruple gate field effect transistor (FET) is provided on the semiconductor-on-insulator or semiconductor-on-insulator (SOI) structure or a bulk semiconductor structure. The silicon substrate is surrounded by a polysilicon material on at least three sides to form a gate. Additionally, the substrate can be surrounded by a fourth side to form a quadruple gate structure. The SOI structure can be comprised of two layers of SOI structures. Interlayer vias can be provided to connect each layer of the two-layer structure.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A method (100) of determining a doping concentration of a semiconductor material (101) includes the steps of moving carriers (102) in the material, wherein a number of carriers is a function of the doping concentration of the material (101). The carriers are deflected (130) toward a surface (110) of the material (101) and an accumulated charge profile on the surface of the material, due to the deflected carriers, is detected (140) and used to calculate (180) the doping concentration across a surface (110) of the material (101).

Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between first and second conductive lines lying adjacent each other along a first plane is provided. A processor controls general operations of the system. A voltage source adapted to apply a bias voltage between the first and second conductive lines is employed to induce a leakage current across the ILD. A light source for illuminating at least a portion of the ILD is used to enhance the leakage current. A magnetic field source applies a magnetic field in a direction orthogonal to the leakage current. The magnetic field deflects carriers in a direction substantially perpendicular to the first plane. A voltage monitor measures a voltage generated across third and fourth conductive lines, the third and fourth conductive lines lying adjacent each other along a second plane which is substantially perpendicular to the first plane. The voltage monitor is operatively coupled to the processor.

Abstract: A process for forming high density isolation for very large scale integration on semiconductor chips, comprising the steps of: orientation-dependent etching a portion of a semiconductor substrate to form protruding features on a surface of the semiconductor substrate; forming a layer of insulation above the etched portion of the semiconductor substrate; implanting atoms and/or ions of a non-conductive material to a first predetermined depth into the insulation layer and a second predetermined depth into the protruding features in the semiconductor substrate to provide a detectible change in material characteristic at that depth; and polishing the insulation layer and protruding features down to a depth determined by detecting the change in material characteristic to thereby remove a top portion of the protruding features to form a first surface on each of a plurality of the protruding features.

Abstract: A method (100) and a system (150) for detecting defects in a dielectric material (112) includes the steps of moving carriers (102) in the dielectric material (112), wherein the number of carriers is a function of whether defects exist in the dielectric material (112). The carriers are then deflected (130) toward a surface (116) of the dielectric material (112) using, for example, a magnetic field (132), and form an accumulated charge profile on the surface (116) of the dielectric material (112). The charge profile is then detected (140) and used to determine (180) the location of defects within the dielectric material (112).

Abstract: A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region.

Abstract: A method for fabricating a memory device is provided. A first polysilicon (poly I) layer is formed over a substrate. Poly I isolation rows are etched into the poly I layer so as to form electrically isolated poly I lines. An oxide-nitride-oxide (ONO) layer is formed over the poly I lines and field oxide portions exposed via the poly I isolation rows. A second polysilicon (poly II) layer is formed over the ONO layer. Poly II isolation rows are etched into the poly II layer so as to form electrically isolated poly II lines, the poly II isolation rows being perpendicular in direction to the poly I isolation rows, the poly II isolation rows exposing portions of the ONO layer. Heavy ions are implanted into portions of the poly I layer via the exposed portions of the ONO layer, wherein the heavy ions disrupt silicon bonds of the poly I layer portions. The exposed portions of the ONO layer and the poly I layer portions are substantially etched away.

Abstract: A quadruple gate field effect transistor (FET) is provided in a silicon-on-insulator or semiconductor-on-insulator (SOI) structure. The silicon substrate is surrounded by a polysilicon material on at least three sides to form a gate. Additionally, the substrate can be surrounded by a fourth side to form a quadruple gate structure. The quadruple gate provides superior current densities across the channel region of the FET. A metal via can be provided to the silicon substrate to avoid floating substrate effects. A flexible support substrate may be coupled to an oxide layer.

Abstract: A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; forming a layer of a first conductive material above the first surface of the semiconductor structure and above the adjacent first insulating region; forming an opening through the layer of first conductive material down to the first insulating region; forming an insulation layer over the layer of first conductive material; forming a layer of a second conductive material above the insulation layer; polishing the layer of second conductive material; and forming a third conductive layer above the layer of second conductive material.

Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between two conductive lines is provided. The system includes a processor for controlling general operations of the system. The system also includes a voltage source adapted to apply a bias voltage between the two conductive lines and induce a leakage current across the ILD. The system employs a light source to illuminate at least a portion of the ILD and enhance the leakage current. A current source is used to measure the induced leakage current, the current source being operatively coupled to the processor. The processor determines the existence of a defect in the ILD based on the measured leakage current.

Abstract: A non-volatile memory device is formed in a substrate, thereby enabling increased densification. Embodiments include forming a trench in a substrate, forming a substantially U-shaped tunnel dielectric layer in the trench, depositing a substantially U-shaped floating gate electrode on the tunnel dielectric layer, forming a dielectric layer on the floating gate electrode extending on the substrate surface and forming a substantially T-shaped control gate electrode filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form source/drain regions extending into the substrate to substantially the same depth, leaving a region containing an impurity of the first conductivity type at the intersection of the trench and substrate surface which prevents shorting between the source/drain region and gate electrodes.