Abstract: Computing system enhancements make container instantiation faster, reduce layer content storage demands, and make more container image formats available. A container instantiation location sends a container image pull request to a container registry, receives an image manifest, sends a layer mount request to the registry instead of a layer content download request, receives a layer mount, optionally repeats for additional layers, creates a union file system spanning the layers, and launches a container process based on the union file system without first downloading all the layer content.

Abstract: A semiconductor structure and a method of fabricating therefor are disclosed. A second contact pad (500) is arranged lateral to a first contact pad (420) in an interconnect structure (400). As a result, during fabrication of the interconnect structure (400), the first contact pad (420) will not be present alone in a large bland area, due to the presence of the second contact pad (500). Thus, a pattern feature for the first contact pad (420) will not be over-resolved, increasing formation accuracy of the first contact pad (420) and thus guaranteeing good electrical transmission performance of the resulting interconnect structure (400).

Abstract: A user equipment (UE) may report capabilities pertaining to UE feedback processing, such as a number of simultaneous feedback reports that can be processed and reported by the UE for various types of feedback. For example, UE feedback processing capability may depend on channel state information (CSI) processing units (CPUs) available to the UE for feedback processing operations (e. g., for performing channel measurements, processing feedback, generating a feedback report, etc.). A UE may report feedback processing capability separately for periodic feedback reporting and for aperiodic feedback reporting, for different types of feedback reporting (e. g., for CSI reporting, for beam management reporting, etc.), etc. As such, a UE may more efficiently report capabilities pertaining to UE feedback processing, and a base station may more efficiently configure UE feedback reporting according to UE feedback processing capability.

Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.

Abstract: A depth estimation from focus method and system includes receiving input image data containing focus information, generating an intermediate attention map by an AI model, normalizing the intermediate attention map into a depth attention map via a normalization function, and deriving expected depth values for the input image data containing focus information from the depth attention map. The AI model for depth estimation can be trained unsupervisedly without ground truth depth maps. The AI model of some embodiments is a shared network estimating a depth map and reconstructing an AiF image from a set of images with different focus positions.

Abstract: A scaling device of a real-time image and a scaling method are disclosed, the scaling device includes a storing unit, a receiving unit, a determining unit, a computing unit, and an outputting unit, wherein the storing unit stores multiple lookup tables respectively corresponding to different scaling algorithms. The receiving unit receives a real-time image from an image outputting device. The determining unit decides a scaling algorithm in accordance with the content of the real-time image and a required scaling ratio, and reads one of the lookup tables from the storing unit based on the decided scaling algorithm. The computing unit performs a scaling process on the real-time image to generate a processed image in accordance with the lookup table read by the determining unit. The outputting unit outputs the processed image.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Abstract: A systolic array includes a plurality of basic computation units arranged in a matrix. A basic computation includes a feature input register configured to store first feature data, a result buffer configured to store first temporary data, a comparator connected to the feature input register and the result buffer, and a control register connected to the feature input register, the result buffer, and the comparator. The comparator is configured to compare the first feature data input with the first temporary data successively. The control register is configured to control the first feature data of the feature input register and the first temporary data to be input to the comparator, output a comparison result to the result buffer and a feature input register of a next basic computation unit, and after sorting, output the first temporary data last stored in the result buffer as a first data result.

Abstract: An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.

Abstract: Embodiments of this application provide an authentication method and apparatus, and a storage system. The method includes: receiving a service request sent by a host, where the service request includes a first account, and the first account is an account complying with a first protocol; determining a second account corresponding to the first account, where the second account is an account complying with a target protocol; and authenticating the second account. An account complying with a non-target protocol is mapped to an account complying with the target protocol for unified user permission authentication.

Abstract: A system includes: 1) a battery configured to provide an input voltage (VIN); 2) switching converter circuitry coupled to the battery, wherein the switching converter circuitry includes a power switch; 3) a load coupled to an output of the switching converter circuitry; and 4) a control circuit coupled to the power switch. The control circuit includes: 1) a switch driver circuit coupled to the power switch; 2) a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and 3) an analog on-time extension circuit configured to extend an on-time of the power switch by gating a second control signal with the first control signal, wherein the second control signal indicates when to turn the power switch off.

Abstract: The present invention is directed to tricyclic compounds, pharmaceutically acceptable compositions comprising compounds of the invention and methods of using said compositions in the treatment of various disorders.

Abstract: Embodiments of improved processes and methods that provide selective etching of silicon nitride are disclosed herein. More specifically, a cyclic, two-step dry etch process is provided to selectively etch silicon nitride layers formed on a substrate, while protecting oxide layers formed on the same substrate. The cyclic, two-step dry etch process sequentially exposes the substrate to: (1) a hydrogen plasma to modify exposed surfaces of the silicon nitride layer and the oxide layer to form a modified silicon nitride surface layer and a modified oxide surface layer, and (2) a halogen plasma to selectively etch silicon nitride by removing the modified silicon nitride surface layer without removing the modified oxide surface layer. The oxide layer is protected from etching during the removal step (i.e., step 2) by creating a crystallized water layer on the oxide layer during the surface modification step (i.e., step 1).

Abstract: A method for accurately positioning a navigation target point includes: selecting a navigation reference with a fixed position, acquiring positions of the navigation reference and the navigation target point in a navigation coordinate system respectively, and calculating a position of the navigation target point relative to the navigation reference, so as to further obtain a position of the navigation target point in a coordinate system of the navigation reference. As long as the navigation reference does not move, the coordinate system of the navigation reference will not change during the entire navigation process, and spatial position coordinates of the navigation target point in the coordinate system of the navigation reference will not be interfered by the navigation coordinate system.

Abstract: The present application discloses a power supply redundancy control system for a GPU server, comprising a power supply redundancy module, a BMC, a CPLD and a GPU module. The power supply redundancy module comprises a first PSU and a second PSU, and the GPU module comprises several GPUs, the first PSU is connected to the CPLD by means of a first bus. The second PSU is connected to the CPLD by means of a second bus. The BMC is connected to the CPLD by means of a first I2C bus and a second I2C bus, and sends heartbeat information to the CPLD. The CPLD is connected to the BMC by means of a third bus and a fourth bus, and the CPLD is connected to the several GPUs by means of a third I2C bus. In the present application, when the BMC is abnormalous or restarted, the CPLD can control the overall power consumption of the server, and can also ensure that the server will not go down, reducing the loss brought to a user due to the BMC being abnormalous or restarted.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: In one example method, a first image including M objects is obtained. For N objects in the M objects, when N is greater than or equal to 2, arrangement orders of the N objects is determined, where an arrangement order of any one of the N objects is determined based on at least one of a scene intent weight, a confidence score, or an object relationship score. The scene intent weight is used to indicate a probability that the any object is searched in a scene corresponding to the first image, the confidence score is a similarity between the any object and an image in an image library, and the object relationship score is used to indicate importance of the any object in the first image. Search results of some or all of the N objects are fed back according to the arrangement orders of the N objects.

Abstract: Provided are an auxiliary alloy casting piece, a high-remanence and high-coercive force NdFeB permanent magnet, and preparation methods thereof. The method for preparing the auxiliary alloy casting piece includes the following steps: providing an auxiliary alloy material including, by mass percentage, 40% to 45% of Pr, 1% to 2% of Co, 0.5% to 1% of Ga, 0.6% to 0.8% of B, 0.1% to 0.2% of V, 0.3% to 0.7% of Ti, and a balance of Fe; smelting the auxiliary alloy material to obtain a smelted material; and subjecting the smelted material to a quick-setting casting to obtain the auxiliary alloy casting piece; where the quick-setting casting includes a refining and a casting in sequence.