Patents by Inventor Yu An

Yu An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11144155
    Abstract: An electronic device adapted to connect to an external device is provided. The electronic device includes an input/output module, a control module, and a touch screen. The control module is electrically connected to the input/output module, and the control module is configured to send a request signal through the input/output module and receive set information corresponding to the request signal through the input/output module. The touch screen is electrically connected to the control module. When the touch screen generates a touch signal in response to a touch behavior, the control module converts the touch signal to a control signal based on the set information, and sends the control signal through the input/output module.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 12, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yu-Sheng Lin, Kuan-Hsin Lee
  • Patent number: 11144859
    Abstract: A computer-implemented method for scheduling an appointment between a user and a resource of a financial institution that includes receiving, at a first computing system associated with the financial institution, a plurality of user preferences regarding the appointment from a user. The user preferences may be received while the user is using a second computing system to conduct a network-based session with the first computing system. The method includes, identifying, by a rules engine, at least one representative of the financial institution based on the user preferences received from the user and scheduling the appointment between the user and the representative based on the identification of the representative.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 12, 2021
    Assignee: WELLS FARGO BANK, N.A.
    Inventors: Kristin Deegan, Karen Ann Yu, Robert M. Caccia, Katherine Joan McGee
  • Patent number: 11146716
    Abstract: A camera module includes a composite base, an optical lens arranged at a first side of the composite base; and a circuit board arranged at a second side of the composite base. The composite base includes a metal frame and a plastic frame. The metal frame includes a plurality of first metal strips connected end to end and at least one second metal strip corresponding extending from part of the plurality of first metal strips. The plastic frame includes a plurality of first plastic strips connected end to end and at least one second plastic strip extending from part of the plurality of first plastic strip. The first plastic strips are fixed to the first metal strips to form a top wall of the composite base, and the second plastic strips are connected to the second metal strips to form a side wall of the composite base.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: October 12, 2021
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.
    Inventors: Jian-Chao Song, Sheng-Jie Ding, Jing-Wei Li, Shin-Wen Chen, Yu-Shuai Li
  • Patent number: 11146933
    Abstract: A cloud computing server includes a memory, a processor, and a communication unit. The memory is configured to store a plurality of activities, a plurality of actions, and an association model that associates the plurality of activities with the plurality of actions. The processor is configured to determine an activity from the plurality of activities by determining a similarity between an upcoming activity and one of the plurality of activities and identify an action based on the activity and the association model. The communication unit is configured to transmit the identified action to a user equipment (UE).
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu Wang, Pei Zheng
  • Patent number: 11145048
    Abstract: An image processing method includes: detecting a plurality of feature lines from a first image captured from a first position; specifying, based on a positional relationship between the plurality of feature lines and a plurality of projection lines generated by projecting each of a plurality of line segments onto the first image, a feature line representing a defective portion of a shape of an object; setting a plurality of candidate positions based on the first position, each of the plurality of candidate positions being a candidate for a second position at which a second image is captured; calculating an evaluation value of each of the plurality of candidate positions; determining any of the plurality of candidate positions based on the evaluation value of each of the plurality of candidate positions; and outputting first information to be used in recognition of the determined candidate position.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Atsunori Moteki, Yu Ishikawa, Toshiyuki Yoshitake
  • Patent number: 11141165
    Abstract: The present disclosure discloses a hemostatic clamp. Two clamping pieces are opened and closed through a ball head pull rod, and a clamping portion at a front end of the hemostatic clamp and a control portion at a rear end are separated through fit of the ball head pull rod with a plastic sleeve and a steel sleeve. Therefore, the hemostatic clamp has the advantages of simple structure, simple operation and high operation stability.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 12, 2021
    Assignee: BEIJING DONGLIN FUSHI MEDICAL DEVICES CO., LTD.
    Inventors: Ling Yu, Chun Yu
  • Patent number: 11144370
    Abstract: The present disclosure provides a communication method for virtual machines, an electronic device, and a non-transitory computer readable storage medium. The communication method for virtual machines suitable for a virtual machine architecture comprises the steps of: transmitting, through a shared link, an interrupt instruction to a second virtual machine by a first virtual machine; reading, in a shared configuration database, an instruction data corresponding to the interrupt instruction by the second virtual machine; and executing the instruction data and transmitting a result data through a virtual control plane to the first virtual machine by the second virtual machine, to exchange the data between the first virtual machine and the second virtual machine through the virtual control plane.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 12, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wei-Chuan Wang, Po-Kai Chuang, Yu-Ting Ting, Chien-Kai Tseng, Tse Ho Lin
  • Patent number: 11145243
    Abstract: A digital-analog conversion circuit includes an arithmetic circuit, a voltage output unit, decoders, and output lines. The arithmetic circuit receives a digital signal of multiple bits, divides the multiple bits into groups of two or more bits, and outputs a logical operation result of each group. The voltage output unit outputs voltages having different values. The decoders receive each voltage and the logical operation result, and outputs an analog signal corresponding to the digital signal. The output lines correspond to the decoders. Each decoder includes switches and selection units. The switches correspond to the voltages. Each switch alternates between output, of a corresponding voltage, to a corresponding output line and non-output, of a corresponding voltage, to a corresponding output line. The selection units correspond to the switches. The selection units receive the logical operation result, and each selection unit controls a corresponding switch based on the logical operation result.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yu Maehashi
  • Patent number: 11145639
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
  • Patent number: 11145660
    Abstract: A dual-port SRAM includes a substrate, first and second active regions over the substrate and oriented lengthwise generally along a first direction; first and second gate electrodes oriented lengthwise generally along a second direction perpendicular to the first direction. The first and second gate electrodes engage the first and second active regions to form first and second pass gate transistors, respectively. The dual-port SRAM further includes a first gate contact disposed over the first gate electrode and electrically connected to the first gate electrode and a first source/drain contact oriented lengthwise generally along the second direction. The first source/drain contact directly contacts source/drain features of the first and second pass gate transistors. A portion of the first gate contact and a portion of the first source/drain contact are at a same vertical level from a top surface of the substrate and are aligned along the first direction.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Dian-Sheg Yu, Ren-Fen Tsui, Jhon Jhy Liaw, Bing-Chian Lin
  • Patent number: 11144485
    Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 12, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
  • Patent number: 11145917
    Abstract: A method for increasing temperature of a battery pack includes determining whether a temperature of a cell in the battery pack is above a lower threshold temperature. The method further includes charging, by a current directly from a charger, a balancing circuit including a resistor in proximity to the cell. The method also includes increasing the temperature of the cell in the battery pack.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Noah Singer, Steven John Ahladas, Xiangfei Yu, Robert K. Mullady
  • Patent number: 11145734
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; a gate structure wrapping each of the semiconductor layers; a spacer structure wrapping an edge portion of each of the semiconductor layers; and a dummy fin structure contacting a sidewall of the gate structure, wherein the dummy fin structure is separated from a sidewall of the spacer structure by a dielectric liner.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11145820
    Abstract: An organic optoelectronic device and a display device including the same, the organic optoelectronic device including: an anode and a cathode facing each other; a light-emitting layer positioned between the anode and the cathode; a hole transport layer positioned between the anode and the light-emitting layer; an auxiliary hole transport layer positioned between the hole transport layer and the light-emitting layer; an electron transport layer positioned between the cathode and the light-emitting layer; and an auxiliary electron transport layer positioned between the electron transport layer and the light-emitting layer, wherein the auxiliary electron transport layer includes at least one kind of first compound represented by chemical formula 1, and the auxiliary hole transport layer includes at least one kind of second compound represented by a combination of a moiety represented by chemical formula 2, a moiety represented by chemical formula 3 and a moiety represented by chemical formula 4.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 12, 2021
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ho-Kuk Jung, Jae-Jin Oh, Dong-Wan Ryu, Su-Jin Han, Gi-Wook Kang, Eui-Su Kang, Youn-Hwan Kim, Hun Kim, Jae-Han Park, Yong-Tak Yang, Eun-Sun Yu, Han-Ill Lee, Woo-Seok Jeong
  • Patent number: 11143355
    Abstract: A multitier folding stand is provided with a rectangular base (1) including two parallel toothed members (11), a transverse groove (12), two cavities (13), two detents (14), two rear bossed holes (15), and a rotatable disc (16); a pivotal platform (2); a bent support (3) pivotably secured to the platform (2); two aligned pivotal arms (4) pivotably secured to the bossed holes (15) respectively and including a lengthwise trough (43); two opposite pivotal support arms (5) including a main part (51), two pivots (52) at two ends of the main part (51) respectively, first and second bearings (53, 54) for securing the pivots (52) to the base (1) respectively, a sliding groove (55) in the main part (51), a first hole (56) through a first end of the sliding groove (55), and a sleeve (58) in the first hole (56); and two opposite pivotal legs (6).
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: October 12, 2021
    Inventor: Cheng Yu Huang
  • Patent number: 11145609
    Abstract: An embodiment of a Doherty amplifier includes a module substrate, first and second surface-mount devices coupled to a top surface of the module substrate, and an impedance inverter line assembly. The first and second surface-mount devices include first and second amplifier dies, respectively. The impedance inverter line assembly is electrically connected between outputs of the first and second amplifier dies. The impedance inverter line assembly includes an impedance inverter line coupled to the module substrate, a first lead of the first surface-mount device coupled between the first amplifier die output and a proximal end of the impedance inverter line, and a second lead of the second surface-mount device coupled between the second amplifier die output and a distal end of the impedance inverter line. According to a further embodiment, the impedance inverter line assembly has a 90 degree electrical length at a fundamental operational frequency of the Doherty amplifier.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Jeffrey Kevin Jones, Elie A. Maalouf, Yu-Ting David Wu, Nick Yang
  • Patent number: 11145808
    Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Minrui Yu, Chando Park, Mang-Mang Ling, Jaesoo Ahn, Chentsau Chris Ying, Srinivas D. Nemani, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11146564
    Abstract: Login authentication in a cloud storage platform includes: receiving, in a cloud storage platform, a user identifier for a user; extracting, based on the user identifier, a domain registered with the cloud storage platform, where each domain registered with the cloud storage platform is associated with an identity authentication endpoint and one or more groups to which users from the domain may be assigned; determining an identity authentication endpoint associated with the extracted domain; providing, to the identity authentication endpoint associated with the extracted domain, login credentials for the user; receiving an identity authorization from the identity authentication endpoint associated with the extracted domain, where the identity authorization includes a plurality of groups for the user; and filtering any groups included in the identity authorization that are not registered with the cloud storage platform.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 12, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Shiva Ankam, Yu Tan
  • Patent number: 11142460
    Abstract: The present disclosure provides a method for repairing defect of graphene, including: firstly introducing a composite fluid containing a reactive compound and a supercritical fluid to a reactor where the graphene powder has been placed, and impregnating the graphene powder with the composite fluid to passivate and repair the defect of graphene, wherein the reactive compound includes carbon, hydrogen, nitrogen, silicon or oxygen element; and separating the composite fluid from the graphene powder, simultaneously using molecular sieves to absorb the graphene from the composite fluid. The present disclosure further provides the graphene powder prepared by the method above. With the method of the present disclosure, it effectively reduces the ratio of the defect of the graphene, increases the content of the graphene, and has less-layer graphene with high thermal conductivity and electrical conductivity.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 12, 2021
    Assignee: XSENSE TECHNOLOGY CORPORATION
    Inventors: Zhen-Yu Li, Po-Min Tu, Chia-Jung Chen, Yeu-Wen Huang
  • Patent number: D933035
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 12, 2021
    Inventor: Yongjie Yu