Patents by Inventor Yu-Bang Nian

Yu-Bang Nian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9787434
    Abstract: A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chi-Feng Lin, Yu-Bang Nian
  • Publication number: 20160173230
    Abstract: A communication device and associated method is provided. The communication device includes: a controller; a packet buffer, configured to store a current packet segment and a previous packet segment of an incoming packet; and a plurality of cyclic redundancy check (CRC) circuits, wherein each CRC circuit is individually fed with a portion of the current packet segment and/or a portion of the previous packet segment in a respective cycle of the incoming packet, and an initial value, wherein the plurality of CRC circuits are arranged in parallel.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Chi-Feng LIN, Yu-Bang NIAN
  • Patent number: 9042505
    Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Chi-Feng Lin, Kung-Yen Hsu, Yu-Bang Nian
  • Publication number: 20150121120
    Abstract: A data transmission apparatus disposed within two network layers operative at different data rates is provided. The data transmission apparatus is coupled to a clock generator which provides a reference clock for a lower network layer and is coupled to a frequency synthesizer with an integer division factor that generates a divided clock for an upper network layer according to the reference clock and the integer division factor. The data transmission apparatus includes a first processing circuit and a second processing circuit. The first processing circuit corresponding to the upper network layer receives and transmits data by using the divided clock as its operation frequency. The second processing circuit corresponding to the lower network layer receives and transmits data from the first processing circuit by using the reference clock as an operation frequency for encoding data. The divided clock is generated from the frequency synthesizer with the integer division factor.
    Type: Application
    Filed: October 29, 2013
    Publication date: April 30, 2015
    Applicant: MEDIATEK INC.
    Inventors: Chi-Feng Lin, Kung-Yen Hsu, Yu-Bang Nian
  • Patent number: 8989318
    Abstract: A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: March 24, 2015
    Assignee: Mediatek Inc.
    Inventors: Kuan-Hua Chao, Tzu-Li Hung, Yu-Bang Nian
  • Patent number: 8707071
    Abstract: One power management method of a communication interface includes: when receiving a command transmitted via the communication interface, checking if a predetermined criterion is met; and when the predetermined criterion is met, controlling the communication interface to enter a power-saving mode before an end of the received command. Another power management method of a communication interface includes: when the communication interface is operated under a power-saving mode, checking if a predetermined criterion of an executed command is met; and when the predetermined criterion is met, controlling the communication interface to leave the power-saving mode.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: April 22, 2014
    Assignee: Mediatek Inc.
    Inventors: Chien-Yu Ting, Tso-Lin Wang, Yu-Bang Nian
  • Publication number: 20130322577
    Abstract: A detecting circuit includes: a first offset generating circuit, arranged to apply a first offset to an input signal pair and accordingly generate a first output signal pair; and a first sampling circuit, coupled to the first offset generating circuit, the first sampling circuit arranged to sample the first output signal pair to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair, and the first sampling circuit is controlled by a first signal that is irrelevant to the input signal pair.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 5, 2013
    Applicant: MEDIATEK INC.
    Inventors: Kuan-Hua Chao, Tzu-Li Hung, Yu-Bang Nian
  • Patent number: 8537937
    Abstract: A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.
    Type: Grant
    Filed: January 9, 2011
    Date of Patent: September 17, 2013
    Assignee: Mediatek Inc.
    Inventors: Kuan-Hua Chao, Tzu-Li Hung, Yu-Bang Nian
  • Publication number: 20120177146
    Abstract: A detecting circuit includes: a first offset generating circuit arranged to apply a first offset to an input signal pair comprising a positive input signal and a negative input signal and accordingly generate a first output signal pair comprising a first positive output signal and a first negative output signal; and a first sampling circuit coupled to the first offset generating circuit, the first sampling circuit arranged to sample a difference in voltage between the first positive output signal and the first negative output signal to generate a first sampling signal, wherein the first sampling signal is utilized to identify a data signal on the input signal pair.
    Type: Application
    Filed: January 9, 2011
    Publication date: July 12, 2012
    Inventors: Kuan-Hua Chao, Tzu-Li Hung, Yu-Bang Nian
  • Publication number: 20120089851
    Abstract: One power management method of a communication interface includes: when receiving a command transmitted via the communication interface, checking if a predetermined criterion is met; and when the predetermined criterion is met, controlling the communication interface to enter a power-saving mode before an end of the received command. Another power management method of a communication interface includes: when the communication interface is operated under a power-saving mode, checking if a predetermined criterion of an executed command is met; and when the predetermined criterion is met, controlling the communication interface to leave the power-saving mode.
    Type: Application
    Filed: April 6, 2011
    Publication date: April 12, 2012
    Inventors: Chien-Yu Ting, Tso-Lin Wang, Yu-Bang Nian