Patents by Inventor Yu-Chan Yen

Yu-Chan Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200412217
    Abstract: Embodiments of the disclosure provide a rotor, a motor, and a driving apparatus. The rotor is defined by laminated electromagnetic steel plates. The electromagnetic steel plate includes a plurality of through hole groups running through the electromagnetic steel plate, and each through hole group includes a plurality of through holes. A central axis of a magnetic pole of the rotor is used as a d axis, and an axis that is 45 degrees from the d axis is used as a q axis, where an outer peripheral surface of the rotor that is between the d axis and the q axis is recessed radially inward relative to an outer peripheral surface of another portion of the rotor, so that the rotor is noncircular when observed in an axial direction.
    Type: Application
    Filed: April 14, 2020
    Publication date: December 31, 2020
    Inventors: Sheng-Chan YEN, Guo-Jhih YAN, Ta-Yin LUO, Yu-Wei HSU, Hsin-Nan LIN, Cheng-Tsung LIU
  • Patent number: 10879129
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10855125
    Abstract: A motor includes a stator including wound multiphase coils and stator slots that accommodate the multiphase coils, and a rotor provided at an inner side of the stator. Poles are provided in a direction of rotation, and sets of flux barriers are provided on the rotor, each of the poles respectively corresponding to a set of the flux barriers. A ratio between a total number of the stator slots and a product of a total number of poles of the rotor and a phase number of the multiphase coils is a non-integer. With the structure of the motor, a torque ripple is reduced while an output torque is kept unchanged.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 1, 2020
    Assignee: NIDEC CORPORATION
    Inventors: Sheng-Chan Yen, Hsin-Nan Lin, Yu-Wei Hsu, Cheng-Tsung Liu
  • Publication number: 20200083110
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20200058765
    Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Patent number: 10504792
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20190372427
    Abstract: A motor includes a rotor including a rotating shaft extending along a center axis, a cylindrical rotor core provided outside the rotating shaft in a radial direction, and two discoid weight plates provided at two ends of the cylindrical rotor core in an axial direction, and a stator opposing the rotor in the radial direction. A radius of each weight plate is smaller than a radius of the rotor core, and a difference between the radius of the rotor core and the radius of each weight plate is larger than an air gap between an outside of the rotor core in the radial direction and an inside of the stator in the radial direction.
    Type: Application
    Filed: February 19, 2018
    Publication date: December 5, 2019
    Applicant: Nidec Corporation
    Inventors: Hsin-Nan LIN, Guo-Jhih YAN, Sheng-Chan YEN, Yu-Wei HSU, Kuo-Min WANG, Cheng-Tsung LIU
  • Publication number: 20190348874
    Abstract: A rotor is located around an outer periphery of a rotation shaft of a motor and rotates together with the rotation shaft. The rotor includes magnetic steel plates laminated in an axial direction and including a through-hole group passing therethrough in the axial direction. The through-hole group includes through-holes each including, as a central line, an imaginary line extending in the radial direction and having an arcuate shape extending from the central line to both sides and radially outward. The through-holes are arranged in the radial direction. Among the through-holes, a radius of curvature of an arcuate radially inner side surface of the radially innermost through-hole is the smallest, and/or a radius of curvature of an arcuate radially outer side surface of the radially outermost through-hole is the largest.
    Type: Application
    Filed: February 19, 2018
    Publication date: November 14, 2019
    Applicant: Nidec Corporation
    Inventors: Sheng-Chan YEN, Yu-Wei HSU, Guo-Jhih YAN, Hsin-Nan LIN, Kuo-Min WANG, Cheng-Tsung LIU
  • Patent number: 10461170
    Abstract: A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chih-Hsin Ko, Chun-Hung Lee, Huan-Just Lin, Hui-Cheng Chang
  • Publication number: 20190165623
    Abstract: A motor includes a stator including wound multiphase coils and stator slots that accommodate the multiphase coils, and a rotor provided at an inner side of the stator. Poles are provided in a direction of rotation, and sets of flux barriers are provided on the rotor, each of the poles respectively corresponding to a set of the flux barriers. A ratio between a total number of the stator slots and a product of a total number of poles of the rotor and a phase number of the multiphase coils is a non-integer. With the structure of the motor, a torque ripple is reduced while an output torque is kept unchanged.
    Type: Application
    Filed: September 26, 2018
    Publication date: May 30, 2019
    Inventors: Sheng-Chan YEN, Hsin-Nan LIN, Yu-Wei HSU, Cheng-Tsung LIU
  • Publication number: 20190122936
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10163723
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9911661
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170365524
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 21, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9812536
    Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee
  • Patent number: 9741621
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170229349
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170154824
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9633907
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9570358
    Abstract: A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth opening in the sacrificial layer, applying a second patterning process to a second photoresist layer to form a fifth opening, a sixth opening, a seventh opening and an eighth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the first and second patterning processes are substantially equal to each other, applying a third patterning process to a third photoresist layer to form a ninth opening, a tenth opening, an eleventh opening and a twelfth opening in the sacrificial layer, wherein distances between two adjacent openings formed from the second and third patterning processes are substantially equal to each other and forming a plurality of nanowires based on the openings.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin