Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate and forming a floating additive layer comprising a floating additive polymer. The floating additive polymer includes a pendant fluorine substituted organic group and one or more of a pendant acid generating group, a pendant base group, a pendant acid labile group, a pendant chromophore group, a pendant developer solubility promoter group, and a pendant acid diffusion control group. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed to form a pattern in the photoresist layer.

Abstract: A method of forming a photoresist pattern includes forming an upper layer including a floating additive polymer over a photoresist layer formed on a substrate. The photoresist layer is selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer, and the upper layer is removed. The floating additive polymer is a siloxane polymer.

Abstract: Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

Abstract: An off-axis light-emitting device and an image capturing module using the same are provided. The off-axis light-emitting device includes a substrate, a light-emitting chip, and an optical element. The substrate has a mounting surface, and the light-emitting chip for generating a light beam has a light output surface. The light-emitting chip is disposed on the assembly surface. The optical element is disposed on the assembly surface and includes a dome portion. The dome portion is arranged in an optical path of the light beam and extends in a first direction to form an elongated shape. The dome portion has a first reference plane that passes through two opposite side surfaces of the dome portion, and the first reference plane is offset from a geometric center of the light-emitting chip in a second direction, so that the light beam passing through the dome portion forms an off-axis projection light.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

Abstract: An application based on nucleotide fragments of Lactobacillus rhamnosus GM-020, to prepare a composition for anti-lipogenesis. The Lactobacillus rhamnosus GM-020 was deposited on Dec. 18, 2003 and has the CCTCC designation number CCTCC M203098. Also provided is a composition containing Lactobacillus rhamnosus GM-020 or nucleotide fragments thereof as effective ingredients for anti-lipogenesis.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from: The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is a linking group.

Abstract: A rehabilitation pedal structure for a hospital bed includes a footboard, a bottom plate pivotally mounted on two sides of the footboard, and two pedals elastically and pivotally mounted on the bottom plate. The footboard is provided with a slot. The bottom plate is pivotally mounted in the slot. The two pedals can be received in the slot. Each of the pedals is electrically connected with one of two monitors, a counter, and a microcontroller. The counter performs a counting action. When the two pedals are respectively stepped or pressed by a user's two feet or hands, the two pedals swing relative to the bottom plate respectively, and the two monitors indicate a swinging number of the two pedals respectively, to facilitate detection of exercise capacity and rehabilitation times of the user's two feet or hands.

Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

Abstract: A linear actuator includes an actuating mechanism, a telescopic structure and a hand rotary releasing structure. The hand rotary releasing structure includes a connecting seat, a clutch seat, a clutch, an adaptor sleeve and a return spring. A peripheral surface of the connecting seat is disposed with multiple clutch troughs. The clutch seat includes multiple engaging troughs. The clutch is disposed between the connecting seat and the clutch seat. The adaptor sleeve is disposed around the clutch and includes multiple spiral troughs. The return spring is disposed around the connecting seat and abuts against the clutch to reduce the activating time and steps of release.

Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate and a vertical transistor. The vertical transistor is disposed on the substrate. The vertical transistor comprises an insulating layer, a source, a drain, a gate insulating layer and a gate. The source and the drain are arranged below and above the insulating layer, and the gate insulating layer surrounds the insulating layer, the source and the drain. The gate covers the gate insulating layer, and the gate insulating layer separates the gate from the source and separates the gate from the drain.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a region. A first gate structure and a sacrificial gate structure are recessed in the substrate and disposed in the region. The sacrificial gate structure is adjacent to the first gate structure. A first contact is electrically connected to the first gate structure. A sacrificial gate masking structure is disposed over the sacrificial gate structure. An upper surface of the sacrificial gate structure is entirely covered by the sacrificial gate masking structure.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.

Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Abstract: A photoresist layer is formed over a wafer. The photoresist layer includes a metallic photoresist material and one or more additives. An extreme ultraviolet (EUV) lithography process is performed using the photoresist layer. The one or more additives include: a solvent having a boiling point greater than about 150 degrees Celsius, a photo acid generator, a photo base generator, a quencher, a photo de-composed base, a thermal acid generator, or a photo sensitivity cross-linker.

Abstract: In a method of manufacturing a semiconductor device, a metallic photoresist layer is formed over a target layer to be patterned, the metallic photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern. The metallic photo resist layer is an alloy layer of two or more metal elements, and the selective exposure changes a phase of the alloy layer.