Patents by Inventor Yu Chang

Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456243
    Abstract: A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: September 27, 2022
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Patent number: 11456266
    Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yu Chang, Ming-Da Cheng, Ming-Hui Weng
  • Patent number: 11456246
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11454251
    Abstract: A fan module holder for holding a fan module generating air flow is disclosed. The holder includes a base, a first wall and a second wall, and a plurality of hooks. The first wall and the second wall extend from opposite ends of the base. The plurality of hooks extends from a top section of the first wall and the second wall and is configured to secure a cooling system. A plurality of apertures is formed as a vent in the first wall. Each of the plurality of hooks includes a protrusion extending therefrom. The second wall includes a cutout. The fan module abuts the base, the first wall, and the second wall of the holder when the holder is in an installed position. The base is generally rectangular and includes a plurality of cylinders.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: September 27, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chun Chang, Ting-Kuang Pao, Yu-Syuan Lin
  • Patent number: 11456170
    Abstract: A cleaning solution includes a first solvent having Hansen solubility parameters 25>?d>13, 25>?p>3, and 30>?h>4; an acid having an acid dissociation constant, pKa, of ?11<pKa<4, or a base having a pKa of 40 > pKa>9.5; and a surfactant. The surfactant is one or more of an ionic surfactant, a polyethylene oxide and a polypropylene oxide, a non-ionic surfactant, and combinations thereof.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Ching-Yu Chang
  • Publication number: 20220302201
    Abstract: Provided is a stacked luminescent device including a plurality of electroluminescent devices and a plurality of conductive lines. The electroluminescent devices are vertically stacked with each other to form a staircase structure on a staircase region. Each electroluminescent device includes a substrate, an encapsulation layer, and a quantum dot light-emitting diode (QLED) device sandwiched between the substrate and the encapsulation layer. The conductive lines are respectively connected to the QLED devices in the electroluminescence devices along the staircase structure. A method of manufacturing the stacked luminescent device is also provided.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 22, 2022
    Applicant: Hongyi Optical Co., Ltd.
    Inventors: Yao-Tang Chang, Tzu Yu Lin
  • Publication number: 20220302061
    Abstract: A semiconductor package and fabricating method thereof are disclosed. The semiconductor package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first area. The pads are formed on a first area of the active surface. Each first bump is formed on the corresponding pad. The second bumps are formed on the second area and each second bump has a first layer and a second layer with different widths. The encapsulation encapsulates the chip and the first and second bumps and is ground to expose the first and second bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased.
    Type: Application
    Filed: August 3, 2021
    Publication date: September 22, 2022
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu CHANG-CHIEN, Hung-Hsin HSU, Nan-Chun LIN
  • Publication number: 20220297383
    Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed during a fabrication of each of the workpiece products; performing photography on each of the melt pools on the powder bed during the fabrication of each of the workpiece products; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
  • Publication number: 20220299628
    Abstract: A frequency modulated continuous wave radar system includes at least one identity tag, respectively disposed next to at least one test subject; and a frequency modulated continuous wave radar identity recognition device, including an identity recognition control module, for controlling a test identity tag of the at least one identity tag to be turned on to generate a specific tag reflection signal corresponding to an identity frequency in response to a chirp signal; and a frequency modulated continuous wave radar, for transmitting the chirp signal and receiving at least one reflection signal of the at least one test subject and the specific tag reflection signal in response to the chirp signal, to calculate and determine that the specific tag reflection signal and a specific reflection signal of the at least one reflection signal are corresponding to an adjacent position information. The specific reflection signal is corresponding to test subject information.
    Type: Application
    Filed: June 21, 2021
    Publication date: September 22, 2022
    Applicant: Wistron Corporation
    Inventors: Yao-Tsung Chang, Yin-Yu Chen, Chuan-Yen Kao
  • Publication number: 20220303045
    Abstract: A wireless communication method for optimizing uplink transmission from a communication partner to a wireless communication device includes the following steps: after receiving an uplink performance estimation, determining uplink adjustment information including resource unit allocation and a target received signal strength indicator according to the uplink performance estimation; generating a target channel quality indicator (CQI) according to previous uplink sounding information and the uplink adjustment information, wherein the previous uplink sounding information indicates the characteristics of the uplink transmission; determining uplink transmission setting including a modulation and coding scheme and dual carrier modulation according to the target CQI and the type of an error correction technique and transmitting a control signal to a communication partner according to the uplink transmission setting; and updating the uplink performance estimation according to a reception signal from the communication
    Type: Application
    Filed: March 11, 2022
    Publication date: September 22, 2022
    Inventors: WEN-YUNG LEE, SHAU-YU CHENG, JHE-YI LIN, CHUN-KAI TSENG, WEI-HSUAN CHANG
  • Publication number: 20220299879
    Abstract: A lithography method is described. The method includes forming a resist layer over a substrate, performing a treatment on the resist layer to form an upper portion of the resist layer having a first molecular weight and a lower portion of the resist layer having a second molecular weight less than the first molecular weight, performing an exposure process on the resist layer, and performing a developing process on the resist layer to form a patterned resist layer.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Ming-Hui WENG, Ching-Yu CHANG
  • Publication number: 20220301822
    Abstract: An embodiment is an apparatus, such as a plasma chamber. The apparatus includes chamber walls and a chamber window defining an enclosed space. A chamber window is disposed between a plasma antenna and a substrate support. A gas delivery source is mechanically coupled to the chamber window. The gas delivery source comprises a gas injector having a passageway, a window at a first end of the passageway, and a nozzle at a second end of the passageway. The nozzle of the gas delivery source is disposed in the enclosed space. A fastening device is mechanically coupled to the gas delivery source. The fastening device is adjustable to adjust a sealing force against the gas injector.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Yung-Shun HSU, Ching-Yu CHANG, Chiao-Kai CHANG, Wai Hong CHEAH, Chien-Fang LIN
  • Publication number: 20220300324
    Abstract: A multi-processor system performs thermal-aware task scheduling and task migration. Based on temperature measurements, the system determines one or more thermal conditions of each processor. The thermal conditions include a present temperature, a historical temperature, a predicted temperature, and thermal headroom of the processor. A scheduler identifies a target processor among the processors based on, at least in part, the one or more thermal conditions of each processor, and assigns a task to be executed by the target processor. For task migration, the system detects that a source processor satisfies a task migration criterion by comparing one or more of the thermal conditions of the source processor with corresponding thresholds. The scheduler identifies a target processor based on, at least in part, one or more of the thermal conditions of each processor, and migrates a task from the source processor to the target processor for execution.
    Type: Application
    Filed: November 11, 2021
    Publication date: September 22, 2022
    Inventors: Ya-Ting Chang, Chih Fu Tsai, Tai Yu Chen, Jia-Ming Chen, Shun-Yao Yang, Ta-Chang Liao, Shengquan Wu, Yu-Chia Chang
  • Publication number: 20220300231
    Abstract: A data transmitting method of a display device, which applies to a transmitting device and the display device. The transmitting device includes a first transmitting module. The display device includes a processing module, a second transmitting module, a storage module, and a display module. The data transmission method includes steps of: select a file on the transmitting device; compress the file to form a compressed file; send the compressed file to the display device via the first transmitting module; receive the compressed file by the second transmitting module of the display device; decompress the compressed file by the processing module to obtain the file; write the file into the storage module by the processing module and correspondingly displaying on the display module based on the file. In this way, a time for transmitting the file could be effectively reduced.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Applicant: WINSTAR DISPLAY CO., LTD.
    Inventors: CHIA-HSIANG NI, WEN-WEI CHUNG, YU-CHANG SONG, CHIEN-CHOU HSU, WEN-HAO LIAO, YU-PIN LIAO
  • Publication number: 20220301937
    Abstract: Semiconductor structures and methods are provided. In one embodiment, a method of the present disclosure includes forming a plurality of semiconductor fins over a substrate, after the forming of the plurality of semiconductor fins, removing an outer semiconductor fin of the plurality of semiconductor fins, and forming a gate structure over the plurality of semiconductor fins. The plurality of semiconductor fins include more than 3 semiconductor fins and the removing recesses a portion of the substrate directly under the outer semiconductor fin.
    Type: Application
    Filed: November 8, 2021
    Publication date: September 22, 2022
    Inventors: Jen-Chun Chou, Ren-Yu Chang, Che-Cheng Chang, Chen-Hsiang Lu
  • Publication number: 20220296099
    Abstract: A monitoring radar and a monitoring and identification method therefor are provided. The monitoring radar may be a physiological information monitoring radar. The monitoring and identification method may be a physiological information monitoring and identification method. The physiological information monitoring radar processes at least one reflected radar signal to obtain a response characteristic and range information corresponding to each of a plurality of to-be-monitored objects and distinguishes the response characteristic of each of the to-be-monitored objects as identification information or physiological information. The physiological information monitoring radar then labels each piece of physiological information according to the range information and the identification information.
    Type: Application
    Filed: July 6, 2021
    Publication date: September 22, 2022
    Inventors: Yao-Tsung CHANG, Yin-Yu CHEN, Chuan-Yen KAO
  • Publication number: 20220301858
    Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
  • Publication number: 20220302393
    Abstract: A halide material having general formula ArMAX is disclosed. The halide material can be processed to an optoelectronic film with a halogenated formamidine and a lead halide, and the optoelectronic film can be applied in the manufacture of an optoelectronic device like a perovskite laser or a PeLED. Experimental data have proved that, the fabricated optoelectronic film shows a property of photoluminescence (PL) peak wavelength adjustable. Moreover, the PL peak wavelength moves from 482 nm to 534 nm with the increase of the content of lead (Pb), halogen (X) and formamidine (FA) in the optoelectronic film Furthermore, experimental data have also indicated that, the fabricated optoelectronic film can be used as a blue emissive layer, a red emissive layer or a green emissive layer, thereby having a significant potential for application in optoelectronics industry.
    Type: Application
    Filed: July 26, 2021
    Publication date: September 22, 2022
    Applicant: National Tsing Hua University
    Inventors: Hao-Wu Lin, Ho-Hsiu Chou, Chih-Li Chang, Chien-Yu Chen, Lin Yang
  • Publication number: 20220302194
    Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Hau Wu, Chih-Kung Chang
  • Patent number: 11447971
    Abstract: An energy dissipation device includes an inner tube, a core tube, an outer tube and a fixing member. The inner tube includes a first protruding structure. The core tube includes a second protruding structure, and the core tube is sleeved outside the inner tube. The outer tube is sleeved outside the core tube. The fixing member is connected to the inner tube, the core tube and the outer tube.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 20, 2022
    Assignee: WELL-LINK INDUSTRY Co., LTD
    Inventors: Chun-Lung Lee, Yi Chang Hsieh, Yu Li Huang