Abstract: A method includes ejecting a metal droplet from a reservoir of a first droplet generator assembled to a vessel; emitting an excitation laser from a laser source to the metal droplet to generate extreme ultraviolet (EUV) radiation; turning off the first droplet generator; cooling down the first droplet generator to a temperature not lower than about 150° C.; dismantling the first droplet generator from the vessel at the temperature not lower than about 150° C.; and assembling a second droplet generator to the vessel.

Abstract: A cable includes: a pair of core wires; a first shielding layer covering the pair of core wires; a second shielding layer covering the first shielding layer, and an outer insulating layer covering the second shielding layer; wherein the first shielding layer is a pure metal tape, and the cable is not provided with a separate ground wire.

Abstract: A method includes following steps. A silicon germanium layer is formed on a substrate. A surface layer of the silicon germanium layer is oxidized to form an interfacial layer comprising silicon oxide and germanium oxide. The interfacial layer is nitridated. A metal gate structure is formed over the nitridated interfacial layer.

Abstract: A cable includes a pair of core wires, a shielding layer covering the pair of core wires, and an outer insulating layer covering the shielding layer, wherein each of the pair of core wires includes an inner conductor and an insulating layer spirally wound around the inner conductor, the insulating layer includes at least two layers, and winding directions of adjacent insulating layers are different.

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

Abstract: A photoresist composition, comprising: a first polymer having one or more acid labile groups; a second polymer having fluorocarbon pendant groups; and metal oxide nanoparticles. The fluorocarbon pendant groups are attached to a main chain of the second polymer via a linking unit R1 of at least one selected from the group consisting of 1-9 carbon unbranched, branched, cyclic, noncylic, saturated, or unsaturated hydrocarbon with optional halogen substituents; —S—; —P—; —P(O2); —C(?O)S—; —C(?O)O—; —O—; —N—; —C(?O)N—; —SO2O—; —SO2S—; —SO—; —SO2—; and —C(?O)—.

Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

Abstract: The wireless communication device includes one or more wireless transceivers and a controller. The one or more wireless transceivers detect(s) one or more first frequency bands of one or more cellular networks, and detect(s) one or more second frequency bands of one or more non-cellular networks. The controller selects one of the first frequency bands and one of the second frequency bands, which do not overlap, and assigns the selected first frequency band to one of the wireless transceivers, thereby enabling one of the wireless transceivers to camp on a cell on the selected first frequency band. Also, the controller assigns the selected second frequency band to one of the wireless transceivers, thereby enabling one of the wireless transceivers to connect to one of the non-cellular networks on the selected second frequency band.

Abstract: A method includes forming a photoresist layer over a substrate, where the photoresist layer includes a polymer blended with a photo-acid generator (PAG), exposing the photoresist layer to a radiation source, and developing the photoresist layer, resulting in a patterned photoresist layer. The PAG is bonded to one or more polarity-enhancing group (PEG), which is configured to increase a dipole moment of the PAG. The exposing may separate the PAG into a cation and an anion, such that a PEG bonded to the cation and a PEG bonded to the anion each increases a polarity of the cation and the anion, respectively.

Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.

Abstract: An object characteristic locating device is provided, which includes a camera module and a processing module. The camera module is configured to capture an image from a front scene. The processing module is configured to perform the following operations: locating a position of an image object in the captured image, and determining a framing range with the image object from the captured image; and preforming image processing on the framing range according to a characteristic of the image object, so as to locate the position of an image characteristic portion of the image object in the captured image.

Abstract: A baculovirus displaying a porcine epidemic diarrhea virus S protein or S1 domain thereof is provided for preventing porcine epidemic diarrhea virus infection.

Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.

Abstract: A training method suitable for a reinforcement learning system with a reward function to train a reinforcement learning model and including: defining at least one reward condition of the reward function; determining at least one reward value range corresponding to the at least one reward condition; searching for at least one reward value from the at least one reward value range by a hyperparameter tuning algorithm; and training the reinforcement learning model according to the at least one reward value.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a resist layer over a material layer, the resist layer includes an inorganic material. The inorganic material includes a plurality of metallic cores and a plurality of first linkers bonded to the metallic cores. The method includes forming a modified layer over the resist layer, and the modified layer includes an auxiliary. The method includes performing an exposure process on the modified layer and the resist layer, and removing a portion of the modified layer and a first portion of the resist layer by a first developer. The first developer includes a ketone-based solvent having a substituted or unsubstituted C6-C7 cyclic ketone, an ester-based solvent having a formula (b), or a combination thereof.

Abstract: A cable includes: a core wire; and an insulating outer layer covering the core wire; where in the core wire including an inner conductor, an inner insulating layer covering the inner conductor, and an outer insulating layer covering the inner insulating layer, the inner insulating layer being made of a material having dielectric constant and loss factor not higher than those of the material of the outer insulating layer, the outer insulating layer being made of a flame-retardant material.

Abstract: This application provides an all-metal downhole power drilling tool based on a multi-stage dual plunger eccentric gear mechanism, which includes a flow distribution shaft, an outer pipe and a multi-stage eccentric gear driving mechanism which are coaxially arranged, the flow distribution shaft is suspended and supported in the outer pipe by the multi-stage eccentric gear driving mechanism. This application provides a novel rotary plunger type power drilling tool hydraulically driven by drilling fluid. The plunger structure is high in processing precision, low in cost and good in plunger type movable sealing effect. A planetary gear train with an eccentric structure is adopted to transmit torque, improving the working efficiency of the power drilling tool. The power drilling tool driven by the multi-stage dual plunger eccentric gear mechanism is of an all-metal structure and can withstand a high temperature environment.

Abstract: A shielding member includes a frame body and an outer cover. Two sides of a first end of the frame body respectively include a first shaft portion. Two sides of the frame body respectively include a first side plate. The frame body is covered by the outer cover. Two sides of a first end of the outer cover respectively include a second shaft portion, and each of the second shaft portions is pivotally connected to the corresponding first shaft portion. Two sides of the outer cover respectively include a second side plate, and each of the second side plates covers an outer side of the corresponding first side plate. Accordingly, the frame body and the outer cover are assembled to form a one-piece metallic shielding member. The structure of the shielding member is simple, the manufacturing for the shielding member is easy, and the cost for manufacturing the shielding member is reduced.

Abstract: A metal-insulator-metal (MIM) capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substrate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.