Abstract: Methods and materials for improving the hardness of a metallic photoresist used in EUV photolithography are disclosed. A metallic cross-linker is used with the metallic photoresist. The cross-linker comprises a metal core and a plurality of ligands. The ligands may comprise at least one vinyl group or at least one acetylene group; or comprise an acrylate; or comprise a cinnamate; or be unable to participate in a crosslinking reaction. Upon radiation exposure, the ligands separate from the metal core, and the metal core can crosslink, or the ligands may crosslink. The resulting photoresist layer has increased hardness and higher EUV light sensitivity, which permits a reduced radiation dosage.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate. A first precursor and a second precursor are combined. The first precursor is an organometallic having a formula: MaRbXc, where M is one or more of Sn, Bi, Sb, In, and Te, R is one or more of a C7-C11 aralkyl group, a C3-C10 cycloalkyl group, a C2-C10 alkoxy group, and a C2-C10 alkylamino group, X is one or more of a halogen, a sulfonate group, and an alkylamino group, and 1?a?2, b?1, c?1, and b+c?4, and the second precursor is one or more of water, an amine, a borane, and a phosphine. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.

Abstract: A an electric deck frame structure (1, 1A) includes: corner lifting vertical posts (10), each having a carrying seat (11) and a retractable rod (12), the carrying seat includes a first connection part (111) having a first electric connection assembly (1133) and a second connection part (116) having a second electric connection assembly (1183); connection pipes (20), connected to the corner lifting vertical posts (10) and having a first opening (21) and a second opening (22); a transformer (30) having an electricity input port (31) arranged corresponding to the first opening (21) and an electricity output port (32) arranged corresponding to the second opening (22), the transformer is hidden in the connection pipe, and a power and signal main cable (40), connected to the electricity output port (32), the first electric connection assembly (1133) and the second electric connection assembly (1183).

Abstract: The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water.

Abstract: Methods and materials for improving the hardness of a metallic photoresist used in EUV photolithography are disclosed. Multiple different additive types are described for use with the metallic photoresist. The additives can be applied to the photoresist as part of existing solutions, or applied as an ingredient in a treatment solution during various steps for applying, patterning, and developing the metallic photoresist. The resulting photoresist layer has increased hardness and higher EUV light sensitivity, which permits a reduced radiation dosage.

Abstract: A charge-discharge method applied to an electronic device for controlling a charging and a discharging of a vehicle, the electronic device communicates with a charging pile. The charge-discharge method comprises collecting operation behavior information of a user with respect to household appliances, inputting the operation behavior information into a preset travel time prediction model to obtain a first driving travel time of the user, determining a first charge-discharge strategy of the vehicle of the user based on the first driving travel time, and transmitting the first charge-discharge strategy to the charging pile. The charging pile charges the vehicle or controls the vehicle to discharge based on the first charge-discharge strategy. An electronic device and a non-transitory storage are also disclosed.

Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Abstract: A resist underlayer composition for extreme ultraviolet lithography is provided. The composition includes a first polymer, a second polymer, an acid generator and a solvent. The first polymer includes a first polymer backbone and an etching resistance enhancement unit covalently bonded to the first polymer backbone via a first linker. The etching resistance enhancement unit includes a silicon-containing unit including silicon-oxygen bonds or a metal-containing unit including metal-oxygen bonds. The second polymer includes a second polymer backbone and a crosslinker unit covalently bonded to the second polymer backbone via a second linker. The crosslinker unit includes one or more crosslinkable groups.

Abstract: Disclosed are a real and virtual identity verification circuit, a system thereof and an electronic transaction method. The circuit is capable of being built in or connected with an electronic device to allow a user to carry out electronic identity verification with his or her unique biological characteristic on a remote server. The real and virtual identity verification circuit comprises a memory unit, an acquisition unit, a processing unit and a communication unit. A verification key code is stored by the memory unit. The acquisition unit acquires the biological characteristic and generates a corresponding biological characteristic code. The processing unit processes the verification key code and the biological characteristic code according to a deal process to generate a corresponding unverified code, and the communication unit transmits the unverified code to the server and awaits a verification result of the electronic identity verification.

Abstract: A light control device, a control method, and a server thereof are provided. The light control device includes a first controller and a second controller. The first controller is disposed on a first circuit board. The first controller is coupled to a selected signal source of multiple signal sources, re-encodes a received control signal, and transmits an encoded control signal through a transmission interface. The second controller is disposed on a second circuit board. The second controller decodes the encoded control signal to generate multiple driving signals. The driving signals are respectively for driving and controlling lighting statuses of multiple lighting components.

Abstract: Semiconductor structures and methods are provided. In one embodiment, a method of the present disclosure includes forming a plurality of semiconductor fins over a substrate, after the forming of the plurality of semiconductor fins, removing an outer semiconductor fin of the plurality of semiconductor fins, and forming a gate structure over the plurality of semiconductor fins. The plurality of semiconductor fins include more than 3 semiconductor fins and the removing recesses a portion of the substrate directly under the outer semiconductor fin.

Abstract: A chip package includes a carrying part, an electronic component, solders, and a filling glue. The carrying part includes an insulating layer and a wiring structure layer disposed on the insulating layer while a first sidewall of the carrying part exposes the wiring structure layer and the insulating layer. The electronic component is disposed on the wiring structure layer. A gap is formed between the electronic component and the wiring structure layer. The solders disposed in the gap are connected to the electronic component and the wiring structure layer. The filling glue covers the wiring structure layer and the side of the electronic component and fills the gap. The filling glue has a second sidewall flush with the first sidewall of the carrying part and a top surface surrounding by the second sidewall and extending from the side of the electronic component to the second sidewall.

Abstract: A light emitting device including an epitaxial structure and a plurality of surface microstructures is provided. The epitaxial structure has a light emitting surface and a surrounding wall surface. The surrounding wall surface surrounds and is connected to the light emitting surface. The plurality of surface microstructures are separately arranged on the light emitting surface along a plurality of directions. The plurality of directions are not perpendicular to the surrounding wall surface. A light emitting device substrate including a plurality of the light emitting device is also provided.

Abstract: A cable includes: a pair of core wires each including an inner conductor and an inner insulating layer covering the inner conductor; an insulating layer covering the pair of core wires; a shielding layer covering the insulating layer; and an outer layer covering the shielding layer; wherein the inner insulating layer includes a first inner insulating layer and a second inner insulating layer, the first inner insulating layer is made of solid material and covers the inner conductor by extrusion molding, the second inner insulating layer is made of foamed material and wraps the first inner insulating layer in a winding way, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer covers the pair of core wires in a winding way, and the second insulating layer covers the first insulating layer by extrusion molding.

Abstract: A photoresist composition comprises an organic polymer and a floatable polymer. The floatable polymer has a lower surface energy than the organic polymer. Upon curing, the floatable polymer forms a surface layer above the photoresist layer formed by the organic polymer. The presence of the surface layer reduces optical flare and chemical flare, thus improving the critical dimension of the features formed in a material layer below the photoresist layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: Provided are a composition and a method for preventing thrombogenesis. The composition includes a conjugate of heparin and a viral capsid protein, wherein the heparin is covalently bonded with the viral capsid protein.