Patents by Inventor Yu-Chang Lai

Yu-Chang Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155845
    Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a layer stack over a substrate, where the layer stack includes alternating layers of a first dielectric material and a word line (WL) material; forming first trenches extending vertically through the layer stack; filling the first trenches, where filling the first trenches includes forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, the second trenches being interleaved with the first trenches; and filling the second trenches, where filling the second trenches includes forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Publication number: 20240114690
    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Publication number: 20240088291
    Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20220388092
    Abstract: A method for forming a bonding structure is provided, including providing a first metal, wherein the first metal has a first absolute melting point. The method includes forming a silver nano-twinned layer on the first metal. The silver nano-twinned layer includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation. The method includes oppositely bonding the silver nano-twinned layer to a second metal. The second metal has a second absolute melting point. The bonding of the silver nano-twinned layer and the second metal is performed at a temperature of 300° C. to half of the first absolute melting point or 300° C. to half of the second absolute melting point.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Tung-Han CHUANG, Po-Ching WU, Pei-Ing LEE, Yu-Chang LAI, Hsing-Hua TSAI, Chung-Hsin CHOU
  • Patent number: 8633857
    Abstract: An antenna structure includes a substrate, a radiation unit, and a metal plate. The radiation unit is disposed on the substrate. The metal plate is separated from the radiation unit for a distance and is electrically isolated with the radiation unit. The metal plate is excited by the radiation unit to generate at least one resonance mode, and includes a hole penetrating the metal plate. Thus, the gain is enhanced, the bandwidth is increased, and multiple resonance modes are provided.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: January 21, 2014
    Assignee: Advanced Connection Technology, Inc.
    Inventors: Yang-Kai Wang, Chien-Hung Chen, Shu-An Yeh, Yu-Chang Lai
  • Publication number: 20120050123
    Abstract: An antenna structure includes a substrate, a radiation unit, and a metal plate. The radiation unit is disposed on the substrate. The metal plate is separated from the radiation unit for a distance and is electrically isolated with the radiation unit. The metal plate is excited by the radiation unit to generate at least one resonance mode, and includes a hole penetrating the metal plate. Thus, the gain is enhanced, the bandwidth is increased, and multiple resonance modes are provided.
    Type: Application
    Filed: November 2, 2010
    Publication date: March 1, 2012
    Applicant: Advanced Connection Technology, Inc.
    Inventors: Yang-Kai Wang, Chien-Hung Chen, Shu-An Yeh, Yu-Chang Lai