Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. An extending direction of a sidewall of the storage element layer is different from an extending direction of a sidewall of the top electrode. A semiconductor device having the memory cell is also provided.

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.

Abstract: A semiconductor structure includes a base layer, a metal-containing gate, a high-k layer and a spacer. The metal-containing gate is disposed over the base layer. The high-k layer is disposed between the base layer and the metal-containing gate. The high-k layer has a protruding portion that protrudes out from a bottom of the metal-containing gate. The spacer is disposed on the sidewall of the metal-containing gate and covers the protruding portion of the high-k layer.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.

Abstract: A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a top electrode, and a variable resistance layer. The first dielectric layer laterally surrounds the bottom electrode. The top electrode is disposed over the bottom electrode and the first dielectric layer. The variable resistance layer is sandwiched between the bottom electrode and the top electrode and between the first dielectric layer and the top electrode. The variable resistance layer exhibits a T-shape in a cross-sectional view.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.

Abstract: A method of forming a semiconductor device is provided. A first ferroelectric inducing layer including Ru is deposited on a substrate. A ferroelectric layer including HfZrO is deposited on the first ferroelectric inducing layer. A second ferroelectric inducing layer including Ru is deposited on the ferroelectric layer, wherein the HfZrO of the ferroelectric layer is in physical contact with the Ru of the first ferroelectric inducing layer and the Ru of the second ferroelectric inducing layer. The second ferroelectric inducing layer, the ferroelectric layer and the first ferroelectric inducing layer are patterned.

Abstract: The present invention discloses a set of novel epigenetic biomarkers for early prediction, treatment response, recurrence and prognosis monitoring of a breast cancer. Aberrant methylation of the genes can be detected in tumor tissues and plasma samples from breast cancer patients but not in normal healthy individual. The present disclosure also discloses primers and probes used herein.

Abstract: A feedback circuit is used for a power supply device. The power supply device includes a primary side circuit and a secondary side circuit. The feedback circuit includes a feedback voltage generation circuit, a base voltage generation circuit, and a compensation signal generation circuit. The feedback voltage generation circuit is electrically connected to the secondary side circuit. The feedback voltage generation circuit generates a feedback voltage according to a bias voltage and an output voltage of the power supply device. The base voltage generation circuit generates a base voltage according to the feedback voltage. The compensation signal generation circuit generates a compensation signal according to the feedback voltage and the base voltage and provides the compensation signal to a controller in the primary side circuit. A voltage value of the feedback voltage is lower than a voltage value of the bias voltage. The voltage value of the feedback voltage varies with the change of the output voltage.

Abstract: A UV LED reactor includes a housing having an inlet, an outlet and a reactor chamber; a UV LED module mounted to the housing configured to emit UV radiation into the reactor chamber having a selected wavelength range and with a selected energy (E); and a heatsink on the UV LED module configured to dissipate heat generated by the UV LED module. The heatsink on the UV LED module includes one or more surfaces in thermal communication or physical contact with the fluid, which improves the efficiency of heat transfer from the heatsink to the fluid and eliminates the need for cooling fans. The UV LED reactor can also include a UV transparent inner tube mounted to the inlet for generating a double UV exposure flow path through the reactor chamber. The UV LED reactor can also include a UV reflective coating on the sidewalls of the housing, or on a separate tube or sleeve mounted to the housing, configured to reflect UV radiation onto the fluid in the reactor chamber.

Abstract: A microphone stand structure includes a stand base, a frame set and a locking unit. The stand base includes a supporting rod, one end of the supporting rod includes a tapered groove and a first hole, the first hole penetrates the bottom of the tapered groove, and the inner wall of the tapered groove includes a first tooth part. A second hole penetrates a tapered convex part, a surface of the tapered convex part includes a second tooth part, the tapered convex part is fitted into the tapered groove, the second tooth part meshes with the first tooth part, and the second hole links to the first hole. The locking unit penetrates the first hole of the supporting rod and the second hole of the fastener.

Abstract: A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.