Patents by Inventor Yu Chao Lin

Yu Chao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210135009
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.
    Type: Application
    Filed: June 18, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE
  • Publication number: 20210126489
    Abstract: A power and signal transmission device for a spindle of a machine tool is provided. The power and signal transmission device includes a spindle fixing portion, a shaft rotating portion, a power transmission component and a signal transmission component. The spindle fixing portion is provided with a power input end, a primary side power induction coil, a secondary side signal induction coil and at least one signal output end. The shaft rotating portion is provided with a joining end surface for bonding to a holder, a secondary side power induction coil and a primary side signal induction coil, and is rotatable with respect to the spindle fixing portion. The power transmission component transmits an electrical energy from the power input end. The signal transmission component transmits a holder signal to the signal output end. Each of the power and signal transmission components includes at least one elastic pogo pin.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 29, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Shiang HUANG, Jenq-Shyong CHEN, Shi-Jie LUO, Shou-Xuan CHANG, Yung-Chao CHAN, Szu-Chia LIN
  • Patent number: 10992178
    Abstract: A power and signal transmission device for a spindle of a machine tool is provided. The power and signal transmission device includes a spindle fixing portion, a shaft rotating portion, a power transmission component and a signal transmission component. The spindle fixing portion is provided with a power input end, a primary side power induction coil, a secondary side signal induction coil and at least one signal output end. The shaft rotating portion is provided with a joining end surface for bonding to a holder, a secondary side power induction coil and a primary side signal induction coil, and is rotatable with respect to the spindle fixing portion. The power transmission component transmits an electrical energy from the power input end. The signal transmission component transmits a holder signal to the signal output end. Each of the power and signal transmission components includes at least one elastic pogo pin.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 27, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Shiang Huang, Jenq-Shyong Chen, Shi-Jie Luo, Shou-Xuan Chang, Yung-Chao Chan, Szu-Chia Lin
  • Publication number: 20210074913
    Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
  • Publication number: 20210066590
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.
    Type: Application
    Filed: October 27, 2020
    Publication date: March 4, 2021
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Publication number: 20210066582
    Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.
    Type: Application
    Filed: January 19, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Publication number: 20200411755
    Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.
    Type: Application
    Filed: January 8, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chao Lin, Carlos H. Diaz, Shao-Ming Yu, Tung-Ying Lee
  • Patent number: 10862031
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Patent number: 10847716
    Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Publication number: 20200365799
    Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying LEE, Shao-Ming YU, Yu-Chao LIN
  • Patent number: 10790124
    Abstract: A method includes forming a coating layer in a dry etching chamber, placing a wafer into the dry etching chamber, etching a metal-containing layer of the wafer, and moving the wafer out of the dry etching chamber. After the wafer is moved out of the dry etching chamber, the coating layer is removed.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Yuan-Ming Chiu, Ming-Ching Chang, Hsin-Yi Tsai, Chao-Cheng Chen
  • Publication number: 20200279998
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
  • Patent number: 10748768
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Patent number: 10665513
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • Publication number: 20200152870
    Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chao LIN, Yuan-Tien TU, Shao-Ming YU, Tung-Ying LEE
  • Patent number: 10541365
    Abstract: The current disclosure describes techniques for patterning a phase-change memory layer. A SiON layer is used as a first hard mask and an electrical conductive protective layer is used as a second hard mask to pattern the phase-change memory layer. An organic BARC layer is sued to improve the photolithography accuracy. The thickness ratio between the organic BARC layer and the hard mask SiON layer and the etching conditions of the hard mask SiON layer are controlled such that the patterned organic BARC layer is completely or near completely resolved simultaneously with the patterning of the hard mask SiON layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu Chao Lin, Jau-Yi Wu, Yu-Sheng Chen, Carlos H. Diaz
  • Publication number: 20190122888
    Abstract: A method includes forming mandrel patterns over a substrate; depositing a spacer layer over the mandrel patterns and onto sidewalls of the mandrel patterns; trimming the spacer layer to reduce a thickness of the spacer layer along a pattern width direction; and etching the spacer layer to expose the mandrel patterns, resulting in a patterned spacer layer on the sidewalls of the mandrel patterns. The trimming of the spacer layer and the etching of the spacer layer are performed in separate processes. After the trimming of the spacer layer and the etching of the spacer layer, the method further includes removing the mandrel patterns.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 25, 2019
    Inventors: Yu Chao Lin, Chao-Cheng Chen, Chun-Hung Lee, Yu-Lung Yang
  • Publication number: 20190109053
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • Patent number: 10236220
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin
  • Publication number: 20190067128
    Abstract: A method includes removing a first portion of a dummy gate structure over a first fin while keeping a second portion of the dummy gate structure over a second fin, where removing the first portion forms a first recess exposing the first fin, forming a first gate dielectric material in the first recess and over the first fin, and removing the second portion of the dummy gate structure over the second fin, where removing the second portion forms a second recess exposing the second fin. The method further includes forming a second gate dielectric material in the second recess and over the second fin, the second gate dielectric material contacting the first gate dielectric material, and filling the first recess and the second recess with a conductive material.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Ming-Ching Chang, Bao-Ru Young, Yu Chao Lin