Patents by Inventor Yu Chao Lin
Yu Chao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140284604Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.Type: ApplicationFiled: June 5, 2014Publication date: September 25, 2014Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
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Publication number: 20140256093Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.Type: ApplicationFiled: March 14, 2013Publication date: September 11, 2014Inventors: Yu-Chao Lin, Cheng-Han Wu, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Publication number: 20140242775Abstract: The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Chao LIN, Chih-Tang PENG, Shun-Hui YANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN
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Patent number: 8791001Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.Type: GrantFiled: March 9, 2009Date of Patent: July 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin
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Patent number: 8765582Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.Type: GrantFiled: September 4, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
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Patent number: 8748989Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.Type: GrantFiled: February 28, 2012Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Chih-Tang Peng, Shun-Hui Yang, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Patent number: 8730070Abstract: A decoding method for unary/kth order exponential Golomb (UEGk) codes is provided. The first step is a receiving step: receiving N bits from an input stream and updating a bit count. If the N bits are all one, the receiving step is re-performed. If the N bits includes zero, a searching step is performed to find a first value based on the bit count. Subsequently, according to the bit count and a threshold value, a remaining bit number M is calculated. A second value is generated based on M remaining bits received from the input stream. Then, the first value and the second value are added, so as to generate an index.Type: GrantFiled: June 11, 2013Date of Patent: May 20, 2014Assignee: MStar Semiconductor, Inc.Inventors: Yao-Hsin Wang, Yu-Chao Lin
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Publication number: 20140134759Abstract: An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process.Type: ApplicationFiled: November 9, 2012Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Chao Lin, Chia-Hao Hsu, Kuo-Yu Wu, Chia-Jen Chen, Chao-Cheng Chen
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Publication number: 20140061655Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
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Publication number: 20130328705Abstract: A decoding method for unary/kth order exponential Golomb (UEGk) codes is provided. The first step is a receiving step: receiving N bits from an input stream and updating a bit count. If the N bits are all one, the receiving step is re-performed. If the N bits includes zero, a searching step is performed to find a first value based on the bit count. Subsequently, according to the bit count and a threshold value, a remaining bit number M is calculated. A second value is generated based on M remaining bits received from the input stream. Then, the first value and the second value are added, so as to generate an index.Type: ApplicationFiled: June 11, 2013Publication date: December 12, 2013Inventors: Yao-Hsin Wang, Yu-Chao Lin
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Patent number: 8551837Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.Type: GrantFiled: February 29, 2012Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin
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Publication number: 20130221443Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Chao LIN, Chih-Tang PENG, Shun-Hui YANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN
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Patent number: 8349680Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.Type: GrantFiled: August 6, 2009Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Ryan Chia-Jen Chen, Su-Chen Lai, Yi-Shien Mor, Yi-Hsing Chen, Gary Shen, Yu Chao Lin
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Patent number: 8273632Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.Type: GrantFiled: October 26, 2011Date of Patent: September 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Patent number: 8258588Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.Type: GrantFiled: April 9, 2010Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Jr Jung Lin, Yih-Ann Lin, Jih-Jse Lin, Chao-Cheng Chen, Ryan Chia-Jen Chen, Weng Chang
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Publication number: 20120108046Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.Type: ApplicationFiled: October 26, 2011Publication date: May 3, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Patent number: 8163625Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.Type: GrantFiled: April 5, 2010Date of Patent: April 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Ann Lin, Hao-Ming Lien, Ryan Chia-Jen Chen, Jr Jung Lin, Yu Chao Lin, Chih-Han Lin
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Patent number: 8148249Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.Type: GrantFiled: March 17, 2009Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu-Chao Lin
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Patent number: 8053323Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.Type: GrantFiled: November 3, 2010Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Ming-Ching Chang, Yih-Ann Lin, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Publication number: 20110031562Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.Type: ApplicationFiled: April 9, 2010Publication date: February 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu Chao LIN, Jr Jung LIN, Yih-Ann LIN, Jih-Jse LIN, Chao-Cheng CHEN, Ryan Chia-Jen CHEN, Weng CHANG