Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A light engine includes an image surface, a projected light surface, a projection lens assembly, and a plurality of folding elements. The image surface has three image areas. The projected light surface has three light sources that provide light with different wavelengths. The plurality of folding elements are arranged along a light emitting axis. The image surface and the projected light surface are substantially in parallel with the light emitting axis, and there is an air gap located between the image surface and the projected light surface. The three light sources respectively correspond to the plurality of folding elements and respectively correspond to the three image areas, and the light emitting axis and the projection lens assembly are disposed on the same optical path.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

Abstract: A transceiver circuit includes a transceiver antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer and a baseband circuit. The transmitter circuit transmits a radio frequency signal corresponding to a radio frequency through the transceiver antenna. The frequency synthesizer provides a first local oscillation signal and a second local oscillation signal having a first local oscillation frequency and a second local oscillation frequency, respectively. The baseband circuit operates in a transmitting mode and a receiving mode. In the transmitting mode, the frequency synthesizer provides the first local oscillation signal, and in the receiving mode, the frequency synthesizer provides the second local oscillation signal, the first local oscillation frequency is a non-integer multiple of the radio frequency, and the second local oscillation frequency is an integer multiple of the radio frequency.

Abstract: A phase locked device includes a digital controlled oscillator circuit, a clock signal generator circuitry, a time to digital converter circuit, and a logic control circuit. The digital controlled oscillator circuit is configured to generate a first clock signal in response to a plurality of digital codes. The clock signal generator circuitry is configured to generate a plurality of second clock signals according to the first clock signal, and to select a third clock signal and a fourth clock signal from the plurality of second clock signals according to a selection signal, in order to generate an output signal. The time to digital converter circuit is configured to detect a delay difference between the output signal and a reference signal, in order to generate the plurality of digital codes. The logic control circuit is configured to generate the selection signal according to the plurality of digital codes.

Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

Abstract: An oscillator includes a voltage-controlled oscillator (VCO) circuit and a processing circuit. The VCO circuit generates an oscillating frequency according to a digital signal, in which the oscillating frequency is a first oscillating frequency if the digital signal has a first signal value. The processing circuit determines a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency, in order to tune the oscillating frequency to a second oscillating frequency. The processing circuit performs an interpolation operation according to a first frequency difference value between the target oscillating frequency and the first oscillating frequency and a second frequency difference value between the second oscillating frequency and the first oscillating frequency to determine a target signal value of the digital signal, in order to adjust the oscillating frequency to the target oscillating frequency.

Abstract: A dual-mode signal transceiver includes a first transmitter circuit, a second transmitter circuit, and a receiver circuit. The first transmitter circuit is configured to operate in a first mode and configured to process a first input signal according to a first oscillating signal, in order to output a first output signal. The second transmitter circuit is configured to operate in a second mode and configured to process a second input signal according to a second oscillating signal, in order to output a second output signal, wherein a frequency of the second oscillating signal is not an integral multiple of a frequency of the first oscillating signal. The receiver circuit is configured to process an external signal associated with one of the first mode and the second mode according to the first oscillating signal, in order to read data associated with the external signal.

Abstract: An oscillator includes a voltage-controlled oscillator (VCO) circuit and a processing circuit. The VCO circuit generates an oscillating frequency according to a digital signal, in which the oscillating frequency is a first oscillating frequency if the digital signal has a first signal value. The processing circuit determines a second signal value of the digital signal according to the first oscillating frequency and a target oscillating frequency, in order to tune the oscillating frequency to a second oscillating frequency. The processing circuit performs an interpolation operation according to a first frequency difference value between the target oscillating frequency and the first oscillating frequency and a second frequency difference value between the second oscillating frequency and the first oscillating frequency to determine a target signal value of the digital signal, in order to adjust the oscillating frequency to the target oscillating frequency.

Abstract: A dual-mode signal transceiver includes a first transmitter circuit, a second transmitter circuit, and a receiver circuit. The first transmitter circuit is configured to operate in a first mode and configured to process a first input signal according to a first oscillating signal, in order to output a first output signal. The second transmitter circuit is configured to operate in a second mode and configured to process a second input signal according to a second oscillating signal, in order to output a second output signal, wherein a frequency of the second oscillating signal is not an integral multiple of a frequency of the first oscillating signal. The receiver circuit is configured to process an external signal associated with one of the first mode and the second mode according to the first oscillating signal, in order to read data associated with the external signal.

Abstract: A phase lock loop (PLL) device with correcting function of loop bandwidth and method thereof is related to the method including generating an output signal by a PLL circuit according to a reference signal and a feedback signal, modulating a feedback coefficient to unlock the feedback signal and the reference signal, detecting two valid crossovers of a phase difference between the reference signal and the feedback signal, calculating an oscillation frequency according to the two valid crossovers, and setting a control parameter of the PLL circuit according to the oscillation frequency. The feedback signal is related to the output signal, and there is the feedback coefficient between the feedback signal and the output signal.

Abstract: A phase lock loop (PLL) device with correcting function of loop bandwidth and method thereof is related to the method including generating an output signal by a PLL circuit according to a reference signal and a feedback signal, modulating a feedback coefficient to unlock the feedback signal and the reference signal, detecting two valid crossovers of a phase difference between the reference signal and the feedback signal, calculating an oscillation frequency according to the two valid crossovers, and setting a control parameter of the PLL circuit according to the oscillation frequency. The feedback signal is related to the output signal, and there is the feedback coefficient between the feedback signal and the output signal.

Abstract: A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.

Abstract: A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal.