Abstract: A microlight emitting diode (LED) system and method of transmitting data are disclosed. The system includes either a first array that contains multiple subarrays or a second array. Each subarray includes multiple independently-addressable single color microLEDs that emit light of different colors and are independently modulated for data communication to another microLED array. The second array contains at least one independently-addressable polychromic microLED. Each polychromic microLED has multiple independently-addressable active regions that emit different colors and that are independently modulated for data transmission to the other microLED array. A photodetector array receives data as multi-color light from the other microLED array and has multiple photodetectors each tuned for a specific color.

Abstract: Secure container use is provided. The method generates respective user group permission identifications associated with image layer staging operations permissions assigned to different user groups as well as a list of the user group permission identifications. Responsive to a request from a user to perform an image layer staging operation, the method verifies whether the user has a user group permission identification in the list of the user group permission identifications. Responsive to verification that the user has a user group permission identification in the list of the user group permission identifications, the requested operation is executed. Responsive to determination that the user does not have a user group permission identification in the list of the user group permission identifications, the requested operation is denied.

Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.

Abstract: An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: The present disclosure discloses tribenzotriquinacene with an axial aryl group and a method for preparing the same. The triphenyltripentacene has a structure shown in formula (1): R1 and R2 are independently hydrogen, a C1-C12 alkyl group, a C1-C12 alkoxy group, a C1-C12 fluoroalkyl group, a C1-C12 fluorine-containing alkoxy group, a C1-C12 ester group, a halogen group, a nitro group, an amine group, a cyano group, or a hydroxy group.

Abstract: A wavelength converter for a shaped surface luminance LED die is described. The wavelength converter produces a peak luminance in a region of the LED die when powered on. The wavelength converter includes a body of a wavelength converting material having a width, a length, and a height. A cross-section of the body in the length direction has a shape such that, when the wavelength converter is installed over the LED die, the height of the body is larger adjacent the region of the LED die that produces the peak luminance.

Abstract: An electrophoretic display with charge balance enhancing circuit includes a control substrate, a charge balance substrate, a charge balance electrode, a display layer arranged on one side of the control substrate, and a charge balance enhancing circuit. The electrophoretic display further includes a plurality of pixel electrodes, a plurality of capacitance electrodes and a plurality of storage capacitors. One end of the storage capacitor is the capacitance electrode. The charge balance enhancing circuit includes a charge-voltage conversion capacitor having a first terminal and a second terminal. The second electrode of the storage capacitor is electrically connected to the first terminal of the charge-voltage conversion capacitor, and the charge balance electrode is electrically connected to the second terminal of the charge-voltage conversion capacitor.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors in a substrate. The substrate comprises a first surface opposite a second surface. An outer isolation structure is disposed in the substrate and laterally surrounds the plurality of photodetectors. The outer isolation structure has a first height. An inner isolation structure is spaced between sidewalls of the outer isolation structure. The inner isolation structure is disposed between adjacent photodetectors in the plurality of photodetectors. The outer isolation structure and the inner isolation structure respectively extend from the second surface toward the first surface. The inner isolation structure comprises a second height less than the first height.

Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.

Abstract: In some aspects, the invention provides a method of treating atherosclerosis in a subject. The method comprises administering to the subject an agent that increases the activity or level of a let-7 miRNA or an agent that decreases activity or level of a TGF? signaling polypeptide in an endothelial cell in the subject. In some embodiments, the subject is administered an additional agent comprising a therapeutically effective amount of rapamycin or any derivative thereof. In some embodiments, the agent is a let-7 miRNA. In some other aspects, the invention provides a pharmaceutical composition comprising a let-7 miRNA. In some embodiments, the let-7 miRNA is encapsulated in a nanoparticle formulated for selective delivery to an endothelial cell.

Abstract: A scheduling method for a switch includes steps as follows. First type protocol flows are sorted according to a sending rate to obtain a plurality of sorted first type protocol flows; a difference of sending rate between each two adjacent of sorted first type protocol flows is calculated to obtain a plurality of differences; N?1 differences are selected from the differences, where each of the N?1 differences is greater than a largest one of remaining differences; a position of each of the N?1 differences between corresponding two adjacent of sorted first type protocol flows is marked to obtain N?1 marked positions; the sorted first type protocol flows are divided into N groups of first type protocol flows according to the N?1 marked positions; each group of the N groups of first type protocol flows is directed to a first queue of the N first queues correspondingly.

Abstract: A semiconductor device includes a first integrated circuit, a bridge die, and a redistribution layer (RDL) structure. The first integrated circuit includes a first interconnect structure, a first passivation layer and a first conductive connector electrically connected to the first interconnect structure and disposed on the first passivation layer. The bridge die bridge die includes a second interconnect structure, a second passivation layer and a second conductive connector electrically connected to the second interconnect structure. The RDL structure is disposed between and electrically connected to the first integrated circuit and the bridge die, wherein the first passivation layer is in direct contact with the first conductive connector, the first conductive connector is in direct contact with the RDL structure, and the first passivation layer is a single layer and includes a first inorganic material.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; a first source/drain region over the first insulating layer, wherein the first source/drain region includes a first semiconductor layer extending continuously over the sidewalls of the first nanostructures, wherein the first semiconductor layer is a first semiconductor material and a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is a second semiconductor material different from the first semiconductor material.

Abstract: A device includes a stack of first nanostructures; a first insulating layer adjacent to the stack of first nanostructures; and a first source/drain region over the first insulating layer, wherein the first source/drain region includes: first semiconductor layers, wherein each first semiconductor layer covers a sidewall of a respective first nanostructure, wherein the first semiconductor layers includes a first semiconductor material; second semiconductor layers, wherein each second semiconductor layer covers a sidewall of a respective first semiconductor layer, wherein the second semiconductor layers includes a second semiconductor material different from the first semiconductor material; and a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer is a third semiconductor material different from the first semiconductor material and different from the second semiconductor material.

Abstract: A load balancing system and method is provided. The load balancing system includes a core network, CPEs (customer premise equipments), user equipments, and a load balancing equipment. The CPEs receive signals from the core network and connect to each other through a network topology. The user equipments are connected to the CPEs. The load balancing equipment is connected to one CPE, and the load balancing equipment confirms a throughput limit of each CPE and includes a data analysis module and a processing unit. The data analysis module receives network parameters between the CPEs and the user equipments, and calculates premise throughputs of the CPEs. The processing unit generates a route control table according to the premise throughputs. According to the route control table, the CPEs adjusts signal transmission between the CPEs and the user equipments to balance the premise throughputs of the CPEs.

Abstract: A full-link reconciliation method based on a snowflake algorithm, an apparatus, a device, and a medium are provided.

Abstract: An electronic device is provided. The electronic device includes a first privacy panel and a second privacy panel disposed on the first privacy panel. The first privacy panel has a first alignment layer and a second alignment layer opposite each other. The second privacy panel has a third alignment layer and a fourth alignment layer opposite each other. The alignment axes of the first alignment layer, the second alignment layer, the third alignment layer and the fourth alignment layer are parallel. The angle between the alignment direction of the first alignment layer and the alignment direction of the third alignment layer is in a range from 160 to 200 degrees. The angle between the alignment direction of the second alignment layer and the alignment direction of the fourth alignment layer is in a range from 160 to 200 degrees.