Patents by Inventor Yu-Chen Chou
Yu-Chen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250191174Abstract: A manufacturing method of an electronic device and a detection device are provided. The manufacturing method of the electronic device includes the following steps. An area condition is stored. A plurality of light-emitting modules are provided. A detection process on each light-emitting module is performed, wherein the detection process includes: lighting up a light-emitting module to be tested; capturing an initial image of the light-emitting module to be tested; performing image processing on the initial image to obtain area information; and comparing the area condition with the area information of the light-emitting module to be tested to determine whether the light-emitting module to be tested belongs to a first group of light-emitting modules or a second group of light-emitting modules. A light-emitting module of the first group of light-emitting modules and a display panel are assembled to obtain the electronic device.Type: ApplicationFiled: November 12, 2024Publication date: June 12, 2025Inventors: Hui-Teng LIN, Yu-Chen CHOU
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Publication number: 20200374507Abstract: A stereo image display apparatus includes a display device, a lens array layer and a shielding unit. The lens array layer is disposed adjacent to a display surface of the display device, and the lens array layer includes a plurality of lenses. The shielding unit is disposed between the display device and the lens array layer, or is disposed on the display device, or is disposed on the lens array layer. The shielding unit includes a plurality of light transmitting regions and at least one light shielding region, the light shielding region is located at a periphery of the light transmitting regions, the light transmitting regions respectively correspond in position to the lenses, and the lens array layer is configured to reconstruct an un-reconstructed image displayed by the display surface as an integral image to produce a stereo image.Type: ApplicationFiled: May 20, 2019Publication date: November 26, 2020Inventors: CHUN-HSIANG YANG, YI-PAI HUANG, CHIH-HUNG TING, KAI-CHIEH CHANG, JUI-YI WU, WEI-AN CHEN, Yu-Chen Chou
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Publication number: 20190195468Abstract: A reflection film including a reflection film substrate and a wavelength conversion layer is provided. The wavelength conversion layer is disposed on the reflection film substrate. The wavelength conversion layer includes a wavelength conversion material, a plurality of nanoparticles and a base material. Since the reflection film of the invention includes the wavelength conversion material and the plurality of nanoparticles, the backlight brightness and the color saturation of the display using the reflection film of the invention are improved.Type: ApplicationFiled: March 8, 2018Publication date: June 27, 2019Applicant: Chunghwa Picture Tubes, LTD.Inventors: Wen-Jiunn Hsieh, Yu-Chen Chou
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Publication number: 20170203691Abstract: The vehicle of no blind spot contains a vehicle body, a number of monitoring devices along the vehicle body's circumference, a number of display devices inside the vehicle electrically connected to at least a corresponding monitoring device. The display device contains a flexible screen. By presenting views around the front, center, and rear pillars, the driver's blind spot problem is resolved and driving safety is enhanced.Type: ApplicationFiled: January 20, 2016Publication date: July 20, 2017Inventors: Yu-Chen Chou, Po-Jen Tsai
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Patent number: 7064428Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.Type: GrantFiled: December 19, 2002Date of Patent: June 20, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6967153Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.Type: GrantFiled: February 10, 2003Date of Patent: November 22, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6927964Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.Type: GrantFiled: August 15, 2003Date of Patent: August 9, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Publication number: 20050161812Abstract: A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.Type: ApplicationFiled: April 14, 2005Publication date: July 28, 2005Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shou Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6877653Abstract: A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.Type: GrantFiled: January 17, 2003Date of Patent: April 12, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6861346Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.Type: GrantFiled: August 14, 2003Date of Patent: March 1, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
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Patent number: 6846719Abstract: A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.Type: GrantFiled: February 20, 2003Date of Patent: January 25, 2005Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6756256Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.Type: GrantFiled: February 20, 2003Date of Patent: June 29, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Publication number: 20040112944Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.Type: ApplicationFiled: August 14, 2003Publication date: June 17, 2004Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
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Publication number: 20040114294Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.Type: ApplicationFiled: August 15, 2003Publication date: June 17, 2004Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6743707Abstract: The present invention provides a bump fabrication process. A wafer is provided with a patterned photoresist layer formed on the wafer. The patterned photoresist layer has a plurality of openings, corresponding to bonding pads. A conductive layer is formed on the photoresist layer and the exposed bonding pads. Afterwards, a sticker film is the provided to lift off the conductive layer on the photoresist layer, while the conductive layer within the openings is not removed. A solder paste is filled into the openings. A reflow step is performed to turn the filled solder paste into globular bumps. At last, the protoresist layer is removed.Type: GrantFiled: December 23, 2002Date of Patent: June 1, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
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Patent number: 6732912Abstract: A solder ball attaching process for attaching solder balls to a wafer is provided. First, an under-ball-metallurgy layer is formed on the active surface of the wafer. Patterned masking layers are sequentially formed over the active surface of the wafer. The masking layers together form a step opening structure that exposes the under-ball-metallic layer. A solder ball is placed on the uppermost masking layer and allowed to roll so that the solder ball drops into the step opening structure by gravity. A reflow process is conducted to join the solder ball and the under-ball-metallurgy layer together. Finally, various masking layers are removed to expose the solder ball on the bonding pad of the wafer.Type: GrantFiled: December 30, 2002Date of Patent: May 11, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6723630Abstract: A solder ball fabrication process for forming solder balls over a wafer having an active layer is provided. A plurality of patterned solder mask layers is sequentially formed over the active surface of the wafer. Each patterned solder mask layer has at least an opening that exposes a solder ball pad on the wafer. The opening of the patterned solder mask layers further away from the solder ball pad is larger in diameter than the opening of the patterned solder mask close to the solder ball pad. Solder material is deposited into the openings and a reflow process is conducted to melt the solder material together so that a solder ball is formed over the solder ball pad.Type: GrantFiled: February 12, 2003Date of Patent: April 20, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
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Patent number: 6720244Abstract: A bump fabrication method is described. The method comprises the steps of providing a wafer having an active surface and a plurality of bonding pads formed on the active surface; respectively forming an under bump metallurgy layer onto the bonding pads, wherein the under bump metallurgy layer includes at least a wetting layer having an oxidized region and positioned at a top layer of the under bump metallurgy layer; patterning a masking layer on the active surface wherein the masking layer is provided with a plurality of openings to expose the wetting layers; removing the oxidized region of the wetting layer using ionic bombardment; fully forming a flux film on the active layer, wherein at least a portion of the flux film covers onto the wetting layer; filling a solder paste into the openings; performing a re-flow process to form a plurality of bumps after the solder paste melts so that the flux film removes the oxidized region of the wetting layer; and removing the masking layer.Type: GrantFiled: February 24, 2003Date of Patent: April 13, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6713320Abstract: A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.Type: GrantFiled: December 30, 2002Date of Patent: March 30, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
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Patent number: 6692581Abstract: A solder paste for fabricating bumps includes a flux and metallic alloy powder. The metallic alloy powder includes a plurality of low eutectic metallic alloy granules, and the size of these metallic alloy granules is 20-60 &mgr;m and the average size of the metallic granules is 35 &mgr;m to 45 &mgr;m.Type: GrantFiled: February 20, 2003Date of Patent: February 17, 2004Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Ching-Fu Horng, Shih-Kuang Chen, Shyh-Ing Wu, Chun-Hung Lin, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao