Abstract: The present disclosure is related to the six isomer structures (OBI-821-1990-V1A, OBI-821-1990-V1B, OBI-821-1990-V2A, OBI-821-1990-V2B, OBI-821-1858-A, and OBI-821-1858-B) of isolated OBI-821 adjuvant and the method for evaluating the quality thereof. The method of the present disclosure adopts hydrophilic interaction liquid chromatography (HILIC) and reverse phase high performance liquid chromatography (RP-HPLC) either alone or in tandem and is able to separate the isomers of OBI-821 adjuvant in the consequent chromatography. Accordingly, the quality of OBI-821 adjuvant can be further evaluated.

Abstract: The present disclosure is related to the six isomer structures (OBI-821-1990-V1A, OBI-821-1990-V1B, OBI-821-1990-V2A, OBI-821-1990-V2B, OBI-821-1858-A, and OBI-821-1858-B) of isolated OBI-821 adjuvant and the method for evaluating the quality thereof. The method of the present disclosure adopts hydrophilic interaction liquid chromatography (HILIC) and reverse phase high performance liquid chromatography (RP-HPLC) either alone or in tandem and is able to separate the isomers of OBI-821 adjuvant in the consequent chromatography. Accordingly, the quality of OBI-821 adjuvant can be further evaluated.

Abstract: A heat sink assembly includes a socket secured on a printed circuit board, an integrated circuit secured on the socket, a heat sink disposed on the integrated circuit, and a resilient retainer clip biasing the heat sink to engage with the socket. An anti-electromagnetic wave device includes a leg engaged with the printed circuit board and a head engaged through a lug of the socket and engaged with one arm of the resilient retainer clip for dissipating the electromagnetic wave that may be transmitted to the integrated circuit.

Abstract: An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree.