Abstract: A leakage-based physical unclonable function (L-PUF) device, a L-PUF array and applications thereof are provided. The L-PUF device includes a precharge circuit, two leaky devices and a sense amplifier. The two leaky devices are electrically connected to the precharge circuit respectively. Each leaky device includes a transistor having a control end electrically connected to ground, a first end electrically connected to the precharge circuit and a second end electrically connected to ground. The sense amplifier is electrically connected to the first end of each of the two leaky devices, and may generate a first output signal and a second output signal. The sense amplifier may switch between a first state and a second state based on a voltage difference between the first leaky device and the second leaky device, which is determined by a leakage current of the first leaky device and a leakage current of the second leaky device.

Abstract: A self-timed readout driver for a leakage-based physical unclonable function (L-PUF) device, a L-PUF array using the same, and applications thereof are provided. The self-timed readout driver includes a precharge transistor, an inverter and a leaky device. The precharge transistor has a control end, a first end and a second end. The inverter is electrically connected to the second end of the precharge transistor. The leaky device having a control end electrically connected to ground, a first end electrically connected to the second end of the precharge transistor, and a second end electrically connected to ground. The control end of the precharge transistor is configured to receive an input signal. The inverter is configured to generate a sense enable (SE) signal. The input signal and the SE signal may be used as two input signals for the L-PUF device.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.

Abstract: A self-timed readout driver for a leakage-based physical unclonable function (L-PUF) device, a L-PUF array using the same, and applications thereof are provided. The self-timed readout driver includes a precharge transistor, an inverter and a leaky device. The precharge transistor has a control end, a first end and a second end. The inverter is electrically connected to the second end of the precharge transistor. The leaky device having a control end electrically connected to ground, a first end electrically connected to the second end of the precharge transistor, and a second end electrically connected to ground. The control end of the precharge transistor is configured to receive an input signal. The inverter is configured to generate a sense enable (SE) signal. The input signal and the SE signal may be used as two input signals for the L-PUF device.

Abstract: A leakage-based physical unclonable function (L-PUF) device, a L-PUF array and applications thereof are provided. The L-PUF device includes a precharge circuit, two leaky devices and a sense amplifier. The two leaky devices are electrically connected to the precharge circuit respectively. Each leaky device includes a transistor having a control end electrically connected to ground, a first end electrically connected to the precharge circuit and a second end electrically connected to ground. The sense amplifier is electrically connected to the first end of each of the two leaky devices, and may generate a first output signal and a second output signal. The sense amplifier may switch between a first state and a second state based on a voltage difference between the first leaky device and the second leaky device, which is determined by a leakage current of the first leaky device and a leakage current of the second leaky device.

Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.

Abstract: A pattern reconfigurable antenna includes a radiator, a first parasitic element, a second parasitic element, a ground plane, a first switch and a second switch. The radiator includes a feed portion and a radiating portion that are interconnected. The first and second parasitic elements are symmetrically located at two opposite sides of the radiating portion, and are closely adjacent to and spaced apart from the radiating portion. The ground plane is located at another side of the radiating portion, and is spaced apart from the first and second parasitic elements. Each of the first and second switches is connected between the ground plane and a respective one of the first and second parasitic elements, and is operable to establish connection between the same.

Abstract: This disclosure relates to methods of treating cancer (e.g., melanoma) with (MI-181).

Abstract: A pattern reconfigurable antenna includes a radiator, a first parasitic element, a second parasitic element, a ground plane, a first switch and a second switch. The radiator includes a feed portion and a radiating portion that are interconnected. The first and second parasitic elements are symmetrically located at two opposite sides of the radiating portion, and are closely adjacent to and spaced apart from the radiating portion. The ground plane is located at another side of the radiating portion, and is spaced apart from the first and second parasitic elements. Each of the first and second switches is connected between the ground plane and a respective one of the first and second parasitic elements, and is operable to establish connection between the same.

Abstract: This disclosure relates to antimitotic compounds, compositions comprising therapeutically effective amounts of these compounds, and methods of using those compounds and compositions in treating hyperproliferative disorders, e.g., cancers and myelodysplastic syndromes.

Abstract: This disclosure relates to antimitotic compounds, compositions comprising therapeutically effective amounts of these compounds, and methods of using those compounds and compositions in treating hyperproliferative disorders, e.g., cancers and myelodysplastic syndromes.