Patents by Inventor Yu-chen Wei
Yu-chen Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240383100Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
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Patent number: 12108412Abstract: A method for uplink transmission performed by a UE is provided. The method includes: receiving a first configured grant configuration that allocates a first PUSCH duration; receiving a second configured grant configuration that allocates a second PUSCH duration, wherein the second PUSCH duration overlaps with the first PUSCH duration; obtaining a first HARQ process ID for the first PUSCH duration, then determining whether a first configured grant timer associated with the first HARQ process ID is running; obtaining a second HARQ process ID for the second PUSCH duration, then determining whether a second configured grant timer associated with the second HARQ process ID is running; and selecting one of the first PUSCH duration and the second PUSCH duration for an uplink transmission based on whether the first configured grant timer is running and whether the second configured grant timer is running.Type: GrantFiled: March 2, 2022Date of Patent: October 1, 2024Assignee: Hannibal IP LLCInventors: Heng-Li Chin, Chia-Hung Wei, Wan-Chen Lin, Yu-Hsin Cheng, Chie-Ming Chou
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Patent number: 12076831Abstract: A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.Type: GrantFiled: April 28, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
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Publication number: 20240203750Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.Type: ApplicationFiled: February 27, 2024Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen WEI, Feng-Inn WU, Tzi-Yi SHIEH
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Patent number: 12009222Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.Type: GrantFiled: December 20, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
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Patent number: 11984324Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.Type: GrantFiled: January 29, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chen Wei, Feng-Inn Wu, Tzi-Yi Shieh
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Publication number: 20230373062Abstract: A chemical mechanical polishing (CMP) apparatus includes a polishing pad located on a top surface of a platen configured to rotate around a vertical axis passing through the platen, a wafer carrier configured to hold a substrate and facing the polishing pad, and an integrated slurry mixer-dispenser including at least two inlet ports configured to receive a respective slurry component, configured to generate slurry by mixing at least two slurry components provided through the at least two inlet ports, and including a dispensation port configured to dispense the slurry over the polishing pad.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Inventors: Yu-Chen Wei, Feng-Inn Wu, You-Shiang Lin, Jiun Ru Huang, Jyun-Jie Wu
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Publication number: 20230278160Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
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Publication number: 20230264317Abstract: A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen WEI, Jheng-Si SU, Shih-Ho LIN, Jen-Chieh LAI, Chun-Chieh CHAN
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Patent number: 11685015Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.Type: GrantFiled: January 28, 2019Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Yuan Yang, Huai-Tei Yang, Yu-Chen Wei, Szu-Cheng Wang, Li-Hsiang Chao, Jen-Chieh Lai, Shih-Ho Lin
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Patent number: 11673223Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.Type: GrantFiled: April 1, 2022Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
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Publication number: 20220219285Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen WEI, Jheng-Si SU, Shih-Ho LIN, Jen-Chieh LAI, Chun-Chieh CHAN
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Publication number: 20220115243Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
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Patent number: 11292101Abstract: A chemical mechanical polishing apparatus is provided. The chemical mechanical polishing apparatus includes a polishing pad, a pad conditioner, a measurement tool, and a controller. The polishing pad is provided in a processing chamber for polishing a wafer placed on the polishing surface of the polishing pad. The pad conditioner is configured to condition the polishing surface. The measurement tool is provided in the processing chamber and configured to measure the downward force of the pad conditioner. The controller is coupled to the pad conditioner and the measurement tool, and is configured to adjust the downward force of the pad conditioner in response to an input from the measurement tool.Type: GrantFiled: February 26, 2018Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
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Patent number: 11251063Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.Type: GrantFiled: October 7, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai
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Patent number: 11239092Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.Type: GrantFiled: April 27, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
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Publication number: 20210407819Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.Type: ApplicationFiled: January 29, 2021Publication date: December 30, 2021Inventors: Yu-Chen Wei, Feng-Inn WU, Tzi-Yi SHIEH
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Publication number: 20210060728Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
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Publication number: 20210028049Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.Type: ApplicationFiled: October 7, 2020Publication date: January 28, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jheng-Si SU, Yu-Chen WEI, Chih-Yuan YANG, Shih-Ho LIN, Jen-Chieh LAI
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Patent number: 10843307Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.Type: GrantFiled: November 9, 2018Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu