Patents by Inventor Yu Cheng

Yu Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190188226
    Abstract: A web page grabbing method is provided. A target web page on a website is grabbed, the target web page including a web page corresponding to a Hypertext Markup Language 5 (H5) content and a web page corresponding to a non-H5 content. The web page corresponding to the H5 content is detected according to web page source code of the target web page. Dynamic rendering is performed on the web page corresponding to the H5 content, to obtain a rendered web page. Content details information corresponding to the H5 content is extracted from the rendered web page.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Zhi Feng CHENG, Bai Yu QIU
  • Publication number: 20190189793
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 20, 2019
    Inventors: CHIH-CHANG CHENG, FU-YU CHU, RUEY-HSIN LIU, KUANG-HSIN CHEN, CHIH-HSIN KO, SHIH-FEN HUANG
  • Publication number: 20190189864
    Abstract: A light source module includes a lighting structure, a light diffusing layer, a wavelength converting layer, and a cover plate. The lighting structure includes a plurality of light emitting elements that are all blue-light emitting elements. The light diffusing layer is disposed on the lighting structure, the wavelength converting layer is disposed on the light diffusing layer, and the cover plate is disposed on the wavelength converting layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 20, 2019
    Inventors: Zhi-Ting Ye, SHYI-MING PAN, YU-CHENG LAN, CHING-HO TIEN
  • Publication number: 20190189228
    Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 20, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Hsiang Lin, Yu-Cheng Hsu
  • Publication number: 20190183099
    Abstract: A direct current pump contains a case, a pumping module, a switch assembly, and a slidable holder. The case is integrally formed, having an accommodation chamber and an opening communicating with the accommodation chamber. The pumping module is received in the accommodation chamber and includes a motor and a pump. The switch assembly is received in the accommodation chamber and is electrically connected to the motor. The switch assembly includes a button for turning on/off the motor. The slidable holder covers onto the opening and is received in the accommodation chamber. The slidable holder includes a receiving portion for a battery assembly to be received therein.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 20, 2019
    Inventor: Yu-Cheng Lin
  • Patent number: 10323122
    Abstract: An electrochromic composition is provided. The electrochromic composition includes 0.5˜10 parts by weight of a first oxidizable polymer, 0.5˜10 parts by weight of a reducible organic compound, 0.5˜20 parts by weight of an electrolyte, and 60˜98.5 parts by weight of a solvent. The first oxidizable polymer is a polymer of 1 molar part of diamine and 0.1˜20 molar parts of dicarboxylic acid, diacyl chloride, or dianhydride, a mixture of the aforementioned polymers, or a copolymer of the aforementioned polymers. An electrochromic element including the aforementioned electrochromic composition is also provided.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: June 18, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Guey-Sheng Liou, Huan-Shen Liu, De-Cheng Huang, Yu-Ruei Kung, Li-Ting Huang, Chyi-Ming Leu
  • Patent number: 10324369
    Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
  • Patent number: 10326005
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Wei-Ting Chen, Yu-Cheng Liu
  • Patent number: 10326089
    Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10326411
    Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chih-Wen Lu, Chih-Hsien Chou, Po-Yu Tseng, Jhih-Siou Cheng
  • Publication number: 20190182981
    Abstract: An outdoor flat panel display assembly is provided to redesign the back cover of a display module where an isolated external circulation structure may be implemented to the back cover of the display module and the back plate of the case. Cold air is introduced into the heat dissipation space within the back cover via external circulating route while heat produced by the backlight, the system circuit board, and by the radiation of the sun can be dissipated through the external circulating route. The external circulation space is completely isolated from the internal space of the case in such a way that the vapor and dust in the introduced cold air are in no way to have contact with the components of the display and the glass of the case.
    Type: Application
    Filed: April 10, 2018
    Publication date: June 13, 2019
    Inventors: Huan-Yuan Huang, Yu-Hua Chang, Wei-Cheng Wang
  • Publication number: 20190180704
    Abstract: A display apparatus and a driving method of a display panel are provided. A display driver drives the display panel so that the adjacent pixels in each of first display segments and each of the second display segments on a scan line have opposite polarities, and two pixels located on junction section of adjacent first display segment and second display segment have the same polarity.
    Type: Application
    Filed: May 4, 2018
    Publication date: June 13, 2019
    Applicant: Au Optronics Corporation
    Inventors: Mei-Chun Cheng, Zun-Yu Wang, Chia-Chu Wang, Yi-Ping Huang, Hao-Ren Gu, Tzu-Han Fang
  • Publication number: 20190179332
    Abstract: Embodiments of the present disclosure disclose a method and apparatus for outputting obstacle information. A specific embodiment of the method comprises: determining a candidate direction information set of a target obstacle point cloud; determining, for each piece of candidate direction information in the candidate direction information set, a target value of the target obstacle point cloud in a direction indicated by the candidate direction information based on the target obstacle point cloud and a smallest circumscribing rectangle of the target obstacle point cloud in the direction indicated by the candidate direction information; defining candidate direction information having a minimum target value in the candidate direction information set as direction information corresponding to the target obstacle cloud point; and outputting the direction information corresponding to the target obstacle cloud point, thereby improving the abundance of content of outputted obstacle information.
    Type: Application
    Filed: September 17, 2018
    Publication date: June 13, 2019
    Inventors: Yiyuan CHENG, Yu MA, Jun WANG
  • Patent number: 10317462
    Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Tzu-Heng Huang
  • Patent number: 10317611
    Abstract: A display device includes a display panel and a backlight module. The display panel is disposed opposite to the backlight module. The backlight module includes a metal substrate, a light emitting element, a circuit layer, an adhesive layer, a reflective element and a light guiding element. The light emitting element is disposed at one side of the circuit layer facing the light guiding element. The adhesive layer is disposed between the circuit layer and a surface of the metal substrate. The reflective element is disposed adjacent to the circuit layer and the adhesive layer and is located on the surface of the metal substrate. The reflective element is disposed between the metal substrate and the light guiding element. A bottom surface of the adhesive layer and at least a part of a bottom surface of the reflective element are located at a same plane.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Innolux Corporation
    Inventors: Kuang-Te Hsia, Chuang-Hsun Chiu, Yu-Cheng Cheng
  • Patent number: 10317950
    Abstract: A pivot assembly adapted to an electronic device is provided. The electronic device includes a first device body including a first pivot side edge and a second device body including a second pivot side edge. The pivot assembly comprises a first pivot pivotally disposed inside the first device body, a second pivot pivotally disposed at the second device body, a first connecting member pivotally connected to the first pivot and the second pivot, a third pivot pivotally disposed at the second device body, a fourth pivot pivotally disposed inside the first device body, and a second connecting member pivotally connected to the third pivot and the fourth pivot. The third pivot is closer to the second pivot side edge relative to the second pivot. The fourth pivot is closer to the first pivot side edge relative to the first pivot.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 11, 2019
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Tsung-Ju Chiang, Yu-Cheng Chang
  • Patent number: 10319856
    Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 11, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10317749
    Abstract: A liquid crystal display panel includes first and second substrates facing each other, a liquid crystal layer between the first and second substrates, at least one pixel electrode including at least one slit and between the first substrate and the liquid crystal layer, and at least one first stripe electrode and at least one second stripe electrode between the second substrate and the liquid crystal layer. The pixel electrode and the slit extend in a first direction. The first stripe electrodes and the second stripe electrodes extend respectively in a second direction not parallel to the first direction. In a vertical projection direction from the second substrate toward the first substrate, at least a portion of the at least one pixel electrode is disposed between at least one first stripe electrode and at least one second stripe electrode, and the first and second stripe electrodes are separated from each other.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Chu Lin, Shu-Hao Huang, Sung-Yu Su, Hsiao-Wei Cheng
  • Patent number: 10318488
    Abstract: A data storage system having data locking and unlocking functions and a method therefor are provided. The data locking and unlocking method includes: when a used capacity of a storage device is equal to or greater than a first threshold, locking a plurality of folders of the foregoing storage device; preventing the folders from being unlocked when the used capacity is greater than or equal to a second threshold; unlocking the locked folders according to a first unlock signal when the used capacity is less than the first threshold; and unlocking the locked folders according to a second unlock signal when the used capacity is between the first threshold and the second threshold. The foregoing second threshold is greater than the first threshold.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 11, 2019
    Assignee: ACCELSTOR LTD.
    Inventors: Yu-Ching Lee, Kun-Cheng Lai, Hann-Huei Chiou, Pan-Lung Tsai
  • Patent number: D851038
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: June 11, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wan-Chen Peng, Ruei-Lin Hung, Ching-Yu Cheng