Patents by Inventor Yu-Cheng Liao

Yu-Cheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020693
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
    Type: Application
    Filed: August 20, 2019
    Publication date: January 21, 2021
    Inventors: Chih-Wei Kuo, Tai-Cheng Hou, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10897131
    Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: January 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 10867811
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Publication number: 20200377717
    Abstract: A polymer composition includes a polyester, a multifunctional compound, and a polymeric compound containing a salt of a metal. The multifunctional compound is one of polyacid, polyanhydride, and the combination thereof. Based on the polymer composition, the metal is present in an amount ranging from 0.01 mol % to 5.0 mol %. Also disclosed herein are an article prepared from the polymer composition and a method for preparing a resin composition from the polymer composition.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 3, 2020
    Inventors: Yu-Cheng LIAO, Mao-Yuan CHIU, Li-Ling CHANG
  • Publication number: 20200328254
    Abstract: The present disclosure discloses a memory cell and a memory device including the same. The memory cell includes a thin film transistor layer, a gate conductive layer, a first heater, a second heater, a phase change layer, and a dielectric layer. The thin film transistor layer includes a channel layer and a first source/drain structure and a second source/drain structure in contact with opposite sides of the channel layer. The gate conductive layer is disposed beneath the gate dielectric layer to control turn-on or turn-off of the channel layer. The first and second heaters are respectively disposed over the first and second source/drain structures. The phase change layer is disposed over the channel layer and in contact with the first and second heaters. The dielectric layer is disposed beneath the phase change layer, and the phase change layer is separated from the channel layer by the dielectric layer.
    Type: Application
    Filed: May 28, 2019
    Publication date: October 15, 2020
    Inventors: Yu-Cheng LIAO, Chun-Chih LIU, Yi-Cheng LEE
  • Publication number: 20200312421
    Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.
    Type: Application
    Filed: July 22, 2019
    Publication date: October 1, 2020
    Inventors: Hsiung-Shih CHANG, Yu-Cheng LIAO, Meng-Hsueh TSAI
  • Patent number: 10764475
    Abstract: A driving mechanism is provided, including a housing, a hollow frame, a holder, and a driving assembly. The frame is fixed to the housing and has a stop surface. The holder is movably disposed in the housing for holding the optical element. The driving assembly is disposed in the housing to drive the holder and the optical element moving along the optical axis of the optical element relative to the frame. Specifically, the stop surface is parallel to the optical axis to contact the holder and restrict the holder in a limit position.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 10755441
    Abstract: A geometric camera calibration system includes an extrinsic iterative closest point (ICP) device that generates an estimated extrinsic matrix by adjusting an initial extrinsic matrix according to first 3D points in camera coordinates; and an intrinsic ICP device that receives 3D points in chessboard coordinates and accordingly generates an error metric between the 3D points in chessboard coordinates and predetermined second reference 3D points. The extrinsic ICP device performs ICP operation to minimize difference between the 3D points in camera coordinates and predetermined first reference 3D points. A current intrinsic matrix is then outputted as an updated intrinsic matrix if a current error metric is not greater than a previous error metric.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 25, 2020
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Ming-Der Shieh, Chun-Wei Chen, Teng-Feng Liao, Yu-Cheng Chen
  • Patent number: 10668763
    Abstract: A PET synthetic paper is composed of a PET substrate and a soft ink absorbing coating coated on the PET substrate. The soft ink absorbing coating includes an acrylic coating and a polyurethane coating embossed on the acrylic coating. The acrylic coating has excellent printability and the polyurethane coating has velvety-soft tactility.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 2, 2020
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wen-Cheng Yang, Ching-Yao Yuan, Chen-An Wu, Yu-Chi Hsieh
  • Publication number: 20200122384
    Abstract: A stretchable modified polyester film, and more particularly to a modified polyester film for in-mold decoration film and having high extensibility, high light transmittance, low shrinkage (high temperature resistance) and the like is provided. The stretchable polyester film is suitable to serve as a stretchable modified polyester film for an in-mold decoration film. The stretchable modified polyester film includes following components: (a) a polyester resin and (b) an acrylic resin.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 23, 2020
    Inventors: TE-CHAO LIAO, Wen-Cheng Yang, CHING-YAO YUAN, CHUN-CHENG YANG, Yu-Chi Hsieh
  • Publication number: 20200122496
    Abstract: A PET synthetic paper is composed of a PET substrate and a soft ink absorbing coating coated on the PET substrate. The soft ink absorbing coating includes an acrylic coating and a polyurethane coating embossed on the acrylic coating. The acrylic coating has excellent printability and the polyurethane coating has velvety-soft tactility.
    Type: Application
    Filed: July 26, 2019
    Publication date: April 23, 2020
    Inventors: TE-CHAO LIAO, Wen-Cheng Yang, CHING-YAO YUAN, Chen-An Wu, Yu-Chi Hsieh
  • Patent number: 10540313
    Abstract: Example implementations relate to computing devices with movable input/output (I/O) connectors. For example, a computing device may include a chassis of the computing device and an I/O connector to connect an I/O device to the computing device. The I/O connector may be movable about an axis relative to the chassis by at least 180 degrees such that the I/O connector is accessible from multiple sides of the chassis.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 21, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shih Chuan Huang, Yu Cheng Wu, Chih Sheng Liao, Hsin Wen Hsu, Benjiman White, William E. Hertling, Mike Whitmarsh
  • Patent number: 10535610
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chia-Liang Liao, Yu-Cheng Tung, Chien-Hao Chen, Chia-Hung Wang
  • Publication number: 20190391362
    Abstract: An optical element driving mechanism is provided, including a base, a holder movably coupled to the base for holding an optical element, a casing, a frame, a driving assembly, and an adhering member. The casing has a top wall and a plurality of side walls extending from the edge of the top wall along an optical axis of the optical element, and the top wall is closer to a light-incident end than the base. The frame is disposed on the top wall and has a frame protrusion extending toward the base. The driving assembly is configured to drive the holder to move relative to the base, and an accommodating space is formed between the base, the frame and the casing. The adhering member is disposed in the accommodating space and configured to directly adhere to the base, the frame, the casing, and the driving assembly.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 26, 2019
    Inventors: Fu-Yuan WU, Kun-Shih LIN, Yu-Huai LIAO, Yu-Cheng LIN, Yen-Cheng CHEN
  • Patent number: 10509193
    Abstract: A driving mechanism includes a frame, a carrying base, and a drive module. The carrying base is disposed in the frame, and includes a carrying body, a first stop element and a second stop element. The carrying body is configured to carry an optical element. The first stop element is disposed on the carrying body, and configured to limit the range of motion of the carrying body in a first direction. The second stop element is disposed on the carrying body, and configured to limit the range of motion of the carrying body in the first direction. The driving module is disposed in the frame, and configured to move the carrying body relative to the frame. The first direction is parallel to the axis of the optical element, and the first stop element is closer to the top portion of the frame than the second stop element.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 17, 2019
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 10475742
    Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 10440841
    Abstract: An electronic device including a housing, a display component and an electronic component is provided. The housing includes a transparent cover and a middle frame, and the transparent cover is assembled to the middle frame. The display component is disposed in the housing. The electronic component is disposed in the housing, wherein the transparent cover has a flat portion and a connecting portion. The connecting portion curvingly extends from a side of the flat portion and includes at least one bonding surface, and a thickness of the flat portion is different from a thickness of the connecting portion.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 8, 2019
    Assignee: HTC Corporation
    Inventors: Chun Tseng, Shih-Po Chien, Yi-Ting Liu, Yu-Jing Liao, I-Cheng Chuang, Chi-Jer Wang, Wen-Shian Lin
  • Publication number: 20190229531
    Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 25, 2019
    Inventors: Yu-Cheng Liao, Ting-Yao Lin, Ping-Chen Chang, Tien-Hao Tang
  • Publication number: 20190213468
    Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Frederick CHEN, Ping-Kun WANG, Shao-Ching LIAO, Chih-Cheng FU, Ming-Che LIN, Yu-Ting CHEN, Seow-Fong (Dennis) LIM
  • Patent number: 10332978
    Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Yu-Cheng Tung, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang