Abstract: The present invention relates to a method for producing recombinant human prethrombin-2 protein and having human ?-thrombin activity by the plant-based expression systems.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: Provided is a semiconductor structure and a formation method therefor. The semiconductor structure includes: a gate structure located on a substrate. The gate structure includes at least two gate conductive layers; the at least two gate conductive layers have the same components and different characteristic parameters; and the characteristic parameter includes at least one of thickness, component content or shape.

Abstract: The disclosure relates to the field of semiconductor technologies, and to a semiconductor structure and a method for forming the same, and a memory. The semiconductor structure of the disclosure includes a substrate, a word line structure, a conductive contact structure and a buffer layer. The substrate includes an active area; the active area includes a channel area, and a source area and a drain area that are respectively distributed on two sides of the channel area; the channel area has a word line groove; the word line structure is located in the word line groove; the conductive contact structure is connected to a top of the drain area; and the buffer layer is located between the conductive contact structure and the word line structure.

Abstract: Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a gate dielectric layer, a metal gate, a hybrid gate, and an isolation layer. A gate trench and a source/drain region positioned on two sides of the gate trench are formed in the base substrate, and the gate dielectric layer covers a bottom wall and a side wall of the gate trench. A top surface of the metal gate is lower than a bottom surface of the source/drain region, and the metal gate includes a conductive layer and a barrier layer positioned between the conductive layer and the gate dielectric layer. The conductive layer is filled in the gate trench, and the conductive layer covers a surface of the barrier layer. The hybrid gate is stacked on the metal gate, and a top surface of the hybrid gate is lower than a surface of the base substrate.

Abstract: A semiconductor structure includes a substrate and a phase-change memory cell located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate, and includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion.

Abstract: The present invention provides a package including a first pad, a die and at least one package ESD component is disclosed. The first pad is configured to receive a signal from a device external to the package. The die comprises a second pad and an internal circuit, wherein the internal circuit is configured to receive the signal from the first pad via the second pad. The at least one ESD component is positioned outside the die.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: A mixed mode memory comprises a memory array, a word line decoder, an intermediary circuit and a reading and writing circuit, wherein the word line decoder is electrically coupled to the memory array, and the intermediary circuit is electrically coupled to the memory array and the writing circuit. The memory array comprises mixed mode memory cells with each cell comprising a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line which controls the reading and writing component group to be conducted or not conducted, and electrically coupled to two bit lines which respectively transmit two data signals. The storage circuit generates two reading response signals based on a reading drive signal. The selection circuit controls the storage circuit to operate in a volatile or non-volatile storage mode based on a selection voltage.

Abstract: A mixed mode memory cell comprises a reading and writing component group, a storage circuit and a selection circuit. The reading and writing component group is electrically coupled to a word line and two bit lines, wherein the two bit lines respectively transmit two data signals. The storage circuit is electrically coupled to the reading and writing component group. The selection circuit is electrically coupled to the reading and writing component group and the storage circuit, and configured to control the storage circuit to operate in a volatile storage mode or a non-volatile storage mode based on a selection voltage.

Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.

Abstract: The present disclosure discloses a memory cell and a memory device including the same. The memory cell includes a thin film transistor layer, a gate conductive layer, a first heater, a second heater, a phase change layer, and a dielectric layer. The thin film transistor layer includes a channel layer and a first source/drain structure and a second source/drain structure in contact with opposite sides of the channel layer. The gate conductive layer is disposed beneath the gate dielectric layer to control turn-on or turn-off of the channel layer. The first and second heaters are respectively disposed over the first and second source/drain structures. The phase change layer is disposed over the channel layer and in contact with the first and second heaters. The dielectric layer is disposed beneath the phase change layer, and the phase change layer is separated from the channel layer by the dielectric layer.

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

Abstract: A polymer composition includes a polyester, a multifunctional compound, and a polymeric compound containing a salt of a metal. The multifunctional compound is one of polyacid, polyanhydride, and the combination thereof. Based on the polymer composition, the metal is present in an amount ranging from 0.01 mol % to 5.0 mol %. Also disclosed herein are an article prepared from the polymer composition and a method for preparing a resin composition from the polymer composition.

Abstract: The present disclosure discloses a memory cell and a memory device including the same. The memory cell includes a thin film transistor layer, a gate conductive layer, a first heater, a second heater, a phase change layer, and a dielectric layer. The thin film transistor layer includes a channel layer and a first source/drain structure and a second source/drain structure in contact with opposite sides of the channel layer. The gate conductive layer is disposed beneath the gate dielectric layer to control turn-on or turn-off of the channel layer. The first and second heaters are respectively disposed over the first and second source/drain structures. The phase change layer is disposed over the channel layer and in contact with the first and second heaters. The dielectric layer is disposed beneath the phase change layer, and the phase change layer is separated from the channel layer by the dielectric layer.

Abstract: A memory test array and a test method thereof are provided. The memory test array includes a first memory array, a second memory array, and a plurality of first common conductive pads. The first memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each of the first common conductive pads has a first end and a second end, and the first ends and the second ends are respectively coupled to the first bit lines and the second bit lines, or respectively coupled to the first word lines and the second word lines. The memory test array of the present disclosure can effectively save the area of the memory test chip and make the test process more efficient.

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

Abstract: A semiconductor structure suitable for ESD protection application is provided. The semiconductor structure includes a first well, a second well, a third well, a first fin, a second fin, an anode, a cathode and a first doping region. The first well and the second well are disposed in the third well. The first fin is disposed on the first well. The second fin is disposed on the second well. The anode is disposed on the first fin. The cathode is disposed on the second fin. The first doping region is disposed under the first fin, and separates the first fin from the first well. The first well, the second well, the first fin and the second fin have a first doping type. The third well and the first doping region have a second doping type.