Patents by Inventor Yu-Cheng Liu
Yu-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250210421Abstract: A power module with detachable function is provided. The power module includes a housing box part, a power component, a housing cover part, and a sensing component. The sensing component is configured to measure parameters of the power component and detachably installed on the housing cover part and the housing box part. When the housing cover part is mounted on the housing box part, the housing cover part and the housing box part can restrict the movement of the sensing component. Thus, a tight fit can be achieved.Type: ApplicationFiled: March 6, 2024Publication date: June 26, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Cheng LIU, Yuan-Cheng HUANG, Shian-Chiau CHIOU, Hsin-Han LIN, Chun-Kai LIU
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Publication number: 20250155472Abstract: A test fixture assembly is for performing a test of a DUT (Device under Test), the DUT includes a plurality of pins exposed on a surface of the DUT, and the test fixture assembly includes a circuit board and a socket unit. The circuit board includes a plurality of test pads, which are exposed on a surface of the circuit board. The socket unit includes a socket base and a plurality of socket probes, which are inserted through the socket base. A first end and a second end of each of the socket probes are respectively exposed on two opposite surfaces of the socket base. Each of the test pads, a corresponding one of the socket probes and a corresponding one of the pins are configured to be linearly arranged along a socket probe direction.Type: ApplicationFiled: November 7, 2024Publication date: May 15, 2025Inventors: HAO LIANG HUNG, CHUN YING HUANG, KUANG TING CHI, YU CHENG LIU
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Publication number: 20250155485Abstract: An antenna test assembly includes a DUT (Device under Test). The DUT includes an antenna module and a circuit board. The antenna module includes a first antenna element, which includes a first antenna pin and a second antenna pin. The circuit board includes a first line and a second line, and two ends of each of the first line and the second line are electrically connected to two metal pads, respectively, exposed on the circuit board. When the antenna test assembly is in an equipment test mode, the first line, the first antenna pin, the second antenna pin and the second line are electrically connected in sequence.Type: ApplicationFiled: October 23, 2024Publication date: May 15, 2025Inventors: HAO LIANG HUNG, CHUN YING HUANG, YU CHENG LIU
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Patent number: 12272595Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.Type: GrantFiled: November 8, 2021Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20240420937Abstract: Embodiments of the present disclosure provide a radio frequency (RF) return device. One example RF return device generally includes a bracket for coupling to a chamber body, a cover coupled to the bracket, and a contact plate coupled to the cover and configured contact a substrate support. Using the RF return device described herein generally enables a reduction in temperature that the RF return device and its various components are exposed to, increasing the durability and lifetime of the RF return device. In addition, the RF return device disclosed herein may block chemicals (e.g., fluorine (F)) used in the process chamber from attacking components included in the RF return device, thereby providing enhanced protection to the RF return device.Type: ApplicationFiled: June 3, 2024Publication date: December 19, 2024Inventors: Yu Cheng LIU, Cheng-yuan LIN, Hsiang AN, Sam S. WANG
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Publication number: 20240047885Abstract: An antenna structure is configured to receive a set of feeding signals via a set of signal feeding nodes to resonate. The antenna structure includes a frame assembly and a radiation assembly. The frame assembly has four side walls. The four side walls form a resonance cavity. Two of the four side walls include two vias, and the two vias are electrically connected to the set of signal feeding nodes, and is configured to receive the set of feeding signals. The radiation assembly is correspondingly connected to the frame assembly. The two of the four side walls are adjacent to each other.Type: ApplicationFiled: October 17, 2022Publication date: February 8, 2024Inventors: KUANG-TING CHI, SHIH-CHI TSENG, YU-CHENG LIU
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Patent number: 11872471Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.Type: GrantFiled: May 3, 2022Date of Patent: January 16, 2024Inventors: Wen-Kuei Liu, Hsiu-Feng Chen, Chao-Hsuan Liu, Yu-Chun Liu, Yi-Shan Liu, Yu-Cheng Liu, Yan-Rui Liu
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Publication number: 20230356061Abstract: A braking mechanism of a wheeled device is provided, including: a main body, configured to be connected to the wheeled device including at least one wheel; an adjusting member, disposed on the main body and including a rod and a first abutting member adjustably positioned on the rod; a braking member, movably disposed on the main body; and an elastic member, abutted between the first abutting member and the braking member so that the braking member is biased by the force of the elastic member toward the at least one wheel to frictionally contact the at least one wheel.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Wen-Kuei LIU, Hsiu-Feng CHEN, Chao-Hsuan LIU, Yu-Chun LIU, Yi-Shan LIU, Yu-Cheng LIU, Yan-Rui LIU
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Patent number: 11776853Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.Type: GrantFiled: January 3, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu
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Publication number: 20230275142Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
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Patent number: 11682716Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.Type: GrantFiled: June 15, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Cheng Chang, Jui-Ping Chuang, Chen-Hsiang Lu, Yu-Cheng Liu, Wei-Ting Chen
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Publication number: 20220386920Abstract: A stretch-deforming electrode includes a stretching portion. The stretching portion has a first stretching range and a second stretching range, in which the stretching portion has a first length variation and a first resistance variation in the first stretching range and a second length variation and a second resistance variation in the second stretching range. The first resistance variation remains substantially unchanged when the first length variation changes, the second resistance variation changes when the second length variation changes. The second resistance variation is represented by R2, the second length variation is represented by L2, and R2=A×L2, in which A is a positive number between 0.05 and 2.Type: ApplicationFiled: March 16, 2022Publication date: December 8, 2022Inventors: Kuan-Jung CHEN, Yu-Cheng LIU
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Patent number: 11363371Abstract: An electronic device includes a main body, a sound guiding tube, a microphone assembly and an adjustment cavity. The device body includes a wall plate. The sound guiding tube is formed on the wall plate of the main body and includes an input end, a first output end and a second output end, and the input end is in communication with the external environment. The microphone assembly is arranged on the main body and in communication with the first output end of the sound guiding tube, and the microphone assembly is acoustically connected to the external environment. The adjustment cavity is arranged in the main body and in communication with the second output end of the sound guiding tube, and the adjustment cavity is acoustically connected to the external environment.Type: GrantFiled: February 1, 2021Date of Patent: June 14, 2022Assignee: Merry Electronics(Shenzhen) Co., Ltd.Inventors: Hung-Wei Chen, Chun-Hung Chang, Shiang-Chun Hsu, Jin-Huang Huang, Yu-Cheng Liu
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Patent number: 11347912Abstract: The invention discloses a prediction method for porous material of electroacoustic devices and prediction system thereof. The method comprises the following steps. The step (A) is to obtain at least one acoustic parameter of a porous material from an electroacoustic device, and the at least one acoustic parameter comprises a flow resistance value, a specific flow resistance value and a flow resistance ratio. The step (B) is to calculate an actual resistance value of the porous material based on the at least one acoustic parameter. Thereafter, the step (C) establishes an equivalent circuit model corresponding to the electroacoustic device based on the structure configuration and material parameters of the electroacoustic device. At last, step (D) introduces the actual impedance value of the porous material into the equivalent circuit model, and calculates the frequency response curve and impedance curve of the electroacoustic device affected by the porous material.Type: GrantFiled: December 26, 2019Date of Patent: May 31, 2022Assignee: FENG CHIA UNIVERSITYInventors: Yu-Cheng Liu, Jin-Huang Huang, Jui-Chu Weng, Tzu-Hsuan Lei
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Publication number: 20220167080Abstract: An electronic device includes a main body, a sound guiding tube, a microphone assembly and an adjustment cavity. The device body includes a wall plate. The sound guiding tube is formed on the wall plate of the main body and includes an input end, a first output end and a second output end, and the input end is in communication with the external environment. The microphone assembly is arranged on the main body and in communication with the first output end of the sound guiding tube, and the microphone assembly is acoustically connected to the external environment. The adjustment cavity is arranged in the main body and in communication with the second output end of the sound guiding tube, and the adjustment cavity is acoustically connected to the external environment.Type: ApplicationFiled: February 1, 2021Publication date: May 26, 2022Applicant: Merry Electronics(Shenzhen) Co., Ltd.Inventors: Hung-Wei Chen, Chun-Hung Chang, Shiang-Chun Hsu, Jin-Huang Huang, Yu-Cheng Liu
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Publication number: 20220130729Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.Type: ApplicationFiled: January 3, 2022Publication date: April 28, 2022Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu
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Publication number: 20220059403Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20220013486Abstract: A semiconductor composite structure includes an electrically conductive bump, and a patterned bonding layer. The electrically conductive bump includes a body portion for being electrically connected to a metal layer of a semiconductor substrate, and a contact portion disposed on the body portion opposite to the metal layer. The patterned bonding layer is disposed on the contact portion opposite to the body portion, and includes an electrically conductive portion and a recess portion depressed relative to the electrically conductive portion. An etching selectivity ratio of the conductive portion relative to the contact portion is greater than 1. A method for making the semiconductor composite structure and a semiconductor device are also disclosed.Type: ApplicationFiled: January 15, 2021Publication date: January 13, 2022Applicant: Powertech Technology Inc.Inventors: Shih-Chang HUANG, Yu-Cheng LIU
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Patent number: 11217458Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.Type: GrantFiled: June 8, 2020Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Hao Chen, Yu-Shu Chen, Yu-Cheng Liu
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Patent number: 11217485Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.Type: GrantFiled: January 14, 2020Date of Patent: January 4, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu