Abstract: An isolated selector and an associated electronic device are provided. The isolated selector receives first data and second data from a first functional circuit and a second functional circuit, respectively, and the isolated selector includes an isolated component, wherein the isolated component receives the first data and generates isolated data according to a control signal and the first data. In addition, the isolated selector selects one of the first data and the second data to be output as output data of the isolated selector. When the isolated selector selects the second data to be output as the output data according to the control signal, the isolated component set the isolated data to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector.

Abstract: A computing device collects a plurality of data samples. Each data sample represents a signal activity of a plurality of signals of the chip. The computing device selects a subset of signals from the plurality of signals as proxies. These proxies are correlated with an actual power consumption of the chip according to a criterion. The computing device trains the power model using signal activities of the plurality of signals as inputs and the actual power consumption as an output. The computing device fine-tunes coefficients of the proxies in the power model. This fine-tuning adjusts an estimation error between an estimated power consumption output by the power model and the actual power consumption.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.

Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

Abstract: A method for removing branches from trained deep learning models is provided. The method includes steps (i)-(v). In step (i), a trained model is obtained. The trained model has a branch structure involving one or more original convolutional layers and a shortcut connection. In step (ii), the shortcut connection is removed from the branch structure. In step (iii), a reparameterization model is built by linearly expanding each of the original convolutional layers into a reparameterization block in the reparameterization model. In step (iv), parameters of the reparameterization blocks are optimized by training the reparameterization model. In step (v), each of the optimized reparameterization blocks is transformed into a reparameterized convolutional layer to form a branchless structure that replaces the branch structure in the trained model.

Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

Abstract: The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.

Abstract: A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

Abstract: A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.

Abstract: A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.

Abstract: A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.

Abstract: A positioning guidance method for tooth brackets is provided. The positioning guidance method includes: obtaining, via an image capturing unit, an oral image; obtaining, via a processor, a position of a candidate tooth according to the contour of a plurality of teeth in the oral image; obtaining, via the processor, a bracket setting position corresponding to the candidate tooth by accessing dental model information from a storage device according to the position of the candidate tooth; obtaining, via the processor, a bracket image corresponding to a bracket from the oral image; and displaying, via the processor, guidance indication on a display unit according to a bracket position corresponding to the bracket image and the bracket setting position.

Abstract: Disclosed is an IC layout design method capable of improving a result of an integrated circuit (IC) layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to an initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining an updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.

Abstract: Disclosed is an IC layout design method capable of improving the result of an IC layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.

Abstract: A positioning guidance method for tooth brackets is provided. The positioning guidance method includes: obtaining, via an image capturing unit, an oral image; obtaining, via a processor, a position of a candidate tooth according to the contour of a plurality of teeth in the oral image; obtaining, via the processor, a bracket setting position corresponding to the candidate tooth by accessing dental model information from a storage device according to the position of the candidate tooth; obtaining, via the processor, a bracket image corresponding to a bracket from the oral image; and displaying, via the processor, guidance indication on a display unit according to a bracket position corresponding to the bracket image and the bracket setting position.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: The present invention discloses a delay difference detection and adjustment device comprising: a first delay circuit including first delay units to receive and transmit a first clock; a second delay circuit including second delay units to receive and transmit a second clock; a storage circuit including storage units, each of which includes a data input end to receive the first clock and an operation clock reception end to receive the second clock, so that the storage circuit is operable to save a plurality of levels of the first clock according to the second clock; a delay control circuit to adjust the delay amount of the second delay circuit; and an analyzing circuit to generate an analysis result according to the cycle and levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first and second delay units.

Abstract: A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to control an embedded oscillator (EMOSC) of the USB device to output a first reference clock compliance USB 2.0 specification and USB 3.0 specification during the initialization phase. After that, a USB 3.0 on-line calibration is performed on the USB device in order to control the EMOSC of the USB device to calibrate a second reference clock during a super-speed mode of USB 3.0 specification.