Patents by Inventor Yu-Cheng Tsai

Yu-Cheng Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110296
    Abstract: An optical coupling module, including a transmission optical fiber and at least one pump optical fiber, is provided. The transmission optical fiber has a central shaft extending along a longitudinal direction and includes a first transmission flat portion, a second transmission flat portion, and a transmission tapered portion. The transmission tapered portion is connected between the first transmission flat portion and the second transmission flat portion. The at least one pump optical fiber extends along the longitudinal direction and includes a pump flat portion and a pump tapered portion. The pump flat portion is disposed on the first transmission flat portion. The pump tapered portion is connected to the pump flat portion. A distance from an outer surface of the pump tapered portion to the central shaft gradually decreases from adjacent to the pump flat portion toward a direction away from the pump flat portion.
    Type: Application
    Filed: November 17, 2023
    Publication date: April 3, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Tsung-Jun Ho, Yu-Cheng Song, Kuo-Teng Tsai, Ying-Hui Yang
  • Publication number: 20250096470
    Abstract: An electronic device includes a casing, an antenna, and a connector. The casing includes a metal layer and a first slot and a second slot located on the metal layer. The metal layer includes a metal connecting segment, a first region, and a second region. The metal connecting segment is located between the first slot and the second slot, and the first region and the second region are separated by the first slot, the second slot, and the metal connecting segment. The antenna is connected to the first region, and the antenna is adapted to resonate at a frequency band. The connector is connected to the second region.
    Type: Application
    Filed: July 2, 2024
    Publication date: March 20, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chang-Hsun Wu, Ming-Huang Chen, Yu-Peng Lin, Hung-Cheng Tsai, Kuo-Yung Chiu, Hsuan-Chi Lin, Chao-Hsu Wu
  • Publication number: 20250076580
    Abstract: A photonic integrated circuit structure includes a semiconductor substrate. A waveguide is disposed above the semiconductor substrate and has an inclined plane. A mirror coating layer is conformally disposed on the inclined plane. A cladding layer covers the waveguide and the mirror coating layer. A hole is disposed in the semiconductor substrate or the cladding layer, and the hole overlaps the inclined plane in a vertical direction. In addition, an optical fiber is disposed in the hole to receive a reflected light from the mirror coating layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ming-Cheng Lo, Jui-Chun Chang, Shih-Chang Huang, Wu-Hsi Lu, Yu-Che Tsai, Shih-Hao Liu, Yen-Shih Ho
  • Patent number: 12205860
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240406124
    Abstract: A computer implemented method for generating a response to a received electronic message. A generative AI is prompted to analyse the electronic message and to generate intent data indicative of an intent associated with the electronic message and data-identifier data indicative of one or more predetermined data identifiers present in the electronic message. The electronic message is analysed to identify and retrieve client data associated with one or more parties associated with the electronic message. The method includes Verifying the retrieved client data includes data corresponding to the generated data-identifier data. If so, query an ERP system with the verified data-identifier data to extract ERP data corresponding to the predetermined data identifiers of which the data-identifier data is indicative, select a response-message template using the intent data, populate the selected response-message template with the ERP data, and present the populated response-message template to a user for approval.
    Type: Application
    Filed: May 21, 2024
    Publication date: December 5, 2024
    Applicant: Sage Global Services Limited
    Inventors: Ben Cunningham, Chandan Kumar, Matthew Shanahan, Peter Horadan, Rohit Kumar, Srijith Rajamohan, Yu-Cheng Tsai
  • Publication number: 20240394285
    Abstract: A computer-implemented chatbot including a prompt generation module, a large language model (LLM) module, and an answer generation module. The prompt generation modules generates an initial prompt based on a prompt template combined with a received user query. The initial prompt includes information source data specifying sources of factual information, conversation history data, and failed response data. The initial prompt is input to the LLM module, which is configured to generate an output and communicate the output to the answer generation module. The answer generation modules determines if the output is a plan to answer a user query. If so, relevant data is retrieved from external database or more APIs specified in the information source data. A further prompt is generated for answering the user query and input to the LLM module. The answer generation module repeats its tasks until a suitable answer to the user query is output.
    Type: Application
    Filed: May 21, 2024
    Publication date: November 28, 2024
    Applicant: Sage Global Services Limited
    Inventors: Ben Cunningham, David Loving, Jordan Earnest, Srijith Rajamohan, Yu-Cheng Tsai
  • Publication number: 20240394512
    Abstract: A computer implemented method of detecting hallucination in a large language model (LLM) output. A message is received. A prompt is generated for an LLM including the message and an instruction to generate an output identifying predetermined content in the message. The prompt is passed through an LLM to generate the output. The output is processed in accordance with a hallucination detection process to identify if any predetermined content identified by the LLM in the output is potentially hallucinated.
    Type: Application
    Filed: May 21, 2024
    Publication date: November 28, 2024
    Applicant: Sage Global Services Limited
    Inventors: Ben Cunningham, David Loving, Jeremiah Edwards, Jordan Earnest, Rohit Kumar, Srijith Rajamohan, Yu-Cheng Tsai
  • Publication number: 20240394600
    Abstract: A system and computer implemented method for detecting hallucination in output of a generative AI system. User input is received specifying a query or task relating to information contained in a data object. A first vector representation of the user input and a second vector representation of the data object are generated. The first and second vector representations are compared to identify parts of the data object which match the query or task. An input is generated for a generative AI system with the user input and the parts of the data object. The input is input to a generative AI system. An output produced by the generative AI system is analysed to determine if the output contains information also present in the data object. If not, an error process is initiated. If so, the output is produced by the generative AI system.
    Type: Application
    Filed: May 21, 2024
    Publication date: November 28, 2024
    Applicant: Sage Global Services Limited
    Inventors: Ben Cunningham, David Loving, Jeremiah Edwards, Jordan Earnest, Rohit Kumar, Srijith Rajamohan, Yu-Cheng Tsai
  • Publication number: 20240394481
    Abstract: A system and computer implemented method for generating validated prompt-templates for generating prompts for instructing large language models (LLMs) to perform specific tasks. An initial prompt is generated instructing an LLM to produce a plurality of candidate prompt-templates. The initial prompt includes an input data type to be included with a prompt generated using a candidate prompt-template, and output data to be produced by an LLM that has processed a prompt generated using a candidate prompt-template. The initial prompt is passed through an LLM to generate candidate prompt-templates. Test prompts are generated, each constructed from a candidate prompt-templates using input data from a set of pre-labelled input data having items of input data and corresponding labels. Each test prompt is passed through a further LLM to generate an output. The output is assessed, and candidate-prompt-templates are selected for subsequent generation of prompts.
    Type: Application
    Filed: May 21, 2024
    Publication date: November 28, 2024
    Applicant: Sage Global Services Limited
    Inventors: Jeremiah Edwards, Rohit Kumar, Srijith Rajamohan, Yu-Cheng Tsai
  • Patent number: 12154939
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240030256
    Abstract: A semiconductor image sensing structure includes a semiconductor substrate having a front side and a back side, a pixel sensor disposed in the semiconductor substrate, a transistor disposed over the front side of the semiconductor substrate, and a reflective structure disposed over the front side of the semiconductor substrate. A gate structure of the transistor and the reflective structure include a same material. A top surface of the gate structure of the transistor and a top surface of the reflective structure are aligned with each other.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: WEI-LIN CHEN, YU-CHENG TSAI, CHUN-HAO CHOU, KUO-CHENG LEE
  • Patent number: 11842378
    Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for analysis of images including wearable items. For example, a method may include obtaining a first set of images, each of the first set of images depicting a product; obtaining a first set of labels associated with the first set of images; training an image segmentation neural network based on the first set of images and the first set of labels; obtaining a second set of images, each of the second set of images depicting a known product; obtaining a second set of labels associated with the second set of images; training an image classification neural network based on the second set of images and the second set of labels; receiving a query image depicting a product that is not yet identified; and performing image segmentation of the query image and identifying the product in the image by performing image analysis.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: December 12, 2023
    Assignee: CAASTLE, INC.
    Inventors: Yu-Cheng Tsai, Dongming Jiang, Georgiy Goldenberg
  • Publication number: 20230369389
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 11769791
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20230041837
    Abstract: A semiconductor device includes an image sensor structure and a periphery device structure. The image sensor structure includes a first semiconductor substrate, a first interconnect structure, a radiation device, a transfer gate transistor electrically coupled to the radiation device, a floating diffusion region electrically coupled to the transfer gate, and a first capacitor disposed in the first interconnect structure. The transfer gate transistor electrically interconnects and disconnects the radiation device and the floating diffusion region. The periphery device structure includes a second interconnect structure disposed on the first interconnect structure, a second semiconductor substrate disposed on the second interconnect structure, a plurality of logic devices disposed in the second semiconductor substrate, and a second capacitor disposed in the second interconnect structure. The first capacitor and the second capacitor are electrically coupled to the floating diffusion region.
    Type: Application
    Filed: January 26, 2022
    Publication date: February 9, 2023
    Inventors: Wei-Lin CHEN, Yu-Cheng TSAI, Chun-Hao CHOU, Kuo-Cheng LEE
  • Publication number: 20220238636
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Application
    Filed: May 5, 2021
    Publication date: July 28, 2022
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 11389698
    Abstract: A fitness equipment control system is provided. The system includes a receiver and a mobile apparatus, and performs the operations: generating a first control signal based on a training course of a user; transmitting the first control signal to the receiver to make the receiver generates a signal which is readable by the fitness equipment according to the first control signal and transmit the readable signal to the fitness equipment; receiving at least one physiological signal from at least one of the wearable devices worn by the user; based on the training course and the at least one physiological signal, generating a second control signal; and when the second control signal is generated, transmitting the second control signal to the receiver, wherein the receiver generates a signal which is readable by the fitness equipment according to the second control signal and transmits it to the fitness equipment.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: July 19, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Ping-Che Yang, Pei-Yuan Tsai, Yu-Cheng Tsai
  • Publication number: 20220179902
    Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for analysis of images including wearable items. For example, a method may include obtaining a first set of images, each of the first set of images depicting a product; obtaining a first set of labels associated with the first set of images; training an image segmentation neural network based on the first set of images and the first set of labels; obtaining a second set of images, each of the second set of images depicting a known product; obtaining a second set of labels associated with the second set of images; training an image classification neural network based on the second set of images and the second set of labels; receiving a query image depicting a product that is not yet identified; and performing image segmentation of the query image and identifying the product in the image by performing image analysis.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 9, 2022
    Inventors: Yu-Cheng TSAI, Dongming JIANG, Georgiy GOLDENBERG
  • Publication number: 20220138590
    Abstract: A model construction system, apparatus, and method are provided. The model construction system includes at least one first source apparatus, at least one second source apparatus, and a model construction apparatus. The model construction apparatus receives a de-identification data set from each first source apparatus, receives a parameter set of a source model from each second source apparatus, generates at least one aligned data set by aligning the de-identification data set according to a predetermined data format, trains an original model to an assisted training model with the aligned data set(s), generates at least one updated parameter set according to the parameter set(s) and an assisted training parameter set, updates the assisted training model with one of the updated parameter set(s), and transmits the updated parameter set(s) to the second source apparatus(es). Each second source apparatus updates the source model according to the corresponding updated parameter set.
    Type: Application
    Filed: November 30, 2020
    Publication date: May 5, 2022
    Inventors: Pei-Yuan TSAI, Yu-Cheng TSAI, Zhi-Guo ZHU, Ping-Che YANG, Chih-Shan LUO