Patents by Inventor YU CHENG YUAN

YU CHENG YUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220201853
    Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create multiple trenches and pads at the same time. After vias are made at the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer with excess conductive metal in the dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 23, 2022
    Inventors: Chih-Liang Chu, Yu Cheng Yuan, Christian Mathias Schmid
  • Publication number: 20220201852
    Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal hard mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create trenches and pads for vias at the same time. After vias are made on the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer in the respective dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.
    Type: Application
    Filed: April 16, 2021
    Publication date: June 23, 2022
    Inventors: CHIH-LIANG CHU, YU CHENG YUAN, CHRISTIAN MATHIAS SCHMID