Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.

Abstract: A self-sterilizing display device is applied to self-sterilizing with a UV light. The self-sterilizing display device includes a display, a light-incident layer, a light source, and a transparent protective layer. The light-incident layer is disposed above the display. The light source is disposed at a periphery of the light-incident layer, and a light-emitting surface of the light source faces to the light-incident layer. The transparent protective layer is disposed between the light-incident layer and the display. Herein, the light source can emit the UV light toward the light-incident layer for sterilizing an outer surface of the self-sterilizing display device by irradiation, and the transparent protective layer can filter out the UV light. Therefore, the surface can be sterilized by UV light, and the UV light can be prevented or reduced from being incident on the display below and damaging the display.

Abstract: A microwave heating sheet includes a substrate and a heating layer disposed on a first surface of the substrate. The heating layer includes a polar solvent that has a boiling point of not less than 100° C. and a polyelectrolyte that is dissolved in the polar solvent.

Abstract: The disclosure provides a freezing device for freezing a liquid mixture and a method using the same. The freezing device includes a container and a tray removably disposed in the container. The tray has a tray plate disposed above a container bottom wall and has a plurality of spaced-apart receptacles for receiving the liquid mixture. When liquid nitrogen is introduced into a region between the tray plate and a container bottom wall, the liquid mixture received in the receptacles is solidified by the liquid nitrogen and is formed into shaped solid coolant pieces.

Abstract: A cooking apparatus for cooking ingredients packaged together in a package is provided. The cooking apparatus includes a cooking device and a barcode reader. The cooking device includes a housing defining a cooking room for accommodating the ingredients therein, a cooking unit for heating contents in the cooking room, and a control module electrically connected to the cooking unit for controlling operation of the cooking unit. The barcode reader is electrically connected to the control module, and scans a barcode on the package representing data related to information about the ingredients, decodes the barcode so as to obtain the data, and transmits the data to the control module that controls operation of the cooking unit based on the information.

Abstract: A microwave heating sheet includes a substrate and a heating layer disposed on a first surface of the substrate. The heating layer includes a polar solvent that has a boiling point of not less than 100° C. and a polyelectrolyte that is dissolved in the polar solvent.

Abstract: A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.

Abstract: An oxygen scavenging formulation comprising an oxidizable polymer resin, a transition metal catalyst, and a photosensitizer selected from one or more carotenoids is provided. The oxygen scavenging formulation does not need an additional triggering agent, or heating or light irradiation to trigger an oxygen scavenging function. A method of reducing oxygen atmosphere in a packaging article is also provided.

Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Abstract: A cooking apparatus for cooking ingredients packaged together in a package is provided. The cooking apparatus includes a cooking device and a barcode reader. The cooking device includes a housing defining a cooking room for accommodating the ingredients therein, a cooking unit for heating contents in the cooking room, and a control module electrically connected to the cooking unit for controlling operation of the cooking unit. The barcode reader is electrically connected to the control module, and scans a barcode on the package representing data related to information about the ingredients, decodes the barcode so as to obtain the data, and transmits the data to the control module that controls operation of the cooking unit based on the information.

Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Abstract: A laminate including a substrate, an antibacterial agent-containing layer on a surface of the substrate, and a moisture triggering layer on the antibacterial agent-containing layer is provided, wherein the antibacterial agent-containing layer contains a volatile antibacterial agent, and the moisture triggering layer contains a hydrophilic polymer such as polyvinylpyrrolidone. The laminate releases a relatively larger amount of anti-bacterial agent in vapor form in a humid environment in comparison with a dry environment.

Abstract: Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Abstract: A laminate including a substrate, an antibacterial agent-containing layer on a surface of the substrate, and a moisture triggering layer on the antibacterial agent-containing layer is provided, wherein the antibacterial agent-containing layer contains a volatile antibacterial agent, and the moisture triggering layer contains a hydrophilic polymer such as polyvinylpyrrolidone. The laminate releases a relatively larger amount of anti-bacterial agent in vapor form in a humid environment in comparison with a dry environment.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.