Patents by Inventor Yu-Chi LU

Yu-Chi LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102194
    Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 28, 2024
    Inventors: Cheng-EN HO, Yu-Lian CHEN, Cheng-Chi WANG, Yu-Jen CHANG, Yung-Sheng LU, Cheng-Yu LEE, Yu-Ming LIN
  • Patent number: 11823908
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20230109915
    Abstract: A device includes a pair of gate spacers on a substrate, and a gate structure on the substrate and between the gate spacers. The gate structure includes an interfacial layer, a metal oxide layer, a nitride-containing layer, a tungsten-containing layer, and a metal compound layer. The interfacial layer is over the substrate. The metal oxide layer is over the interfacial layer. The nitride-containing layer is over the metal oxide layer. The tungsten-containing layer is over the nitride-containing layer. The metal compound layer is over the tungsten-containing layer. The metal compound layer has a different material than a material of the tungsten-containing layer.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Patent number: 11568578
    Abstract: A method for generating goods modeling data comprises obtaining a platform image associated with a platform, a plurality of first goods images and a plurality of second goods images, wherein the first goods images and the second goods images correspond to different viewing angles respectively, and an image synthesis processing is performed according to the platform image and at least one of the first goods images and the second goods images to generate a synthesized image. The synthesized image includes a plurality of adjacent or partially overlapping image areas which correspond to at least many of the viewing angles. The image areas include a first and a second image areas. The first image area includes one of the first goods images or one of the second goods images. The second image area includes one of the first goods images or one of the second goods images.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang Hong Lin, Po Hsuan Hsiao, Guan Rong Lin, Yu-Chi Lu
  • Publication number: 20220207784
    Abstract: A method for generating goods modeling data comprises obtaining a platform image associated with a platform, a plurality of first goods images and a plurality of second goods images, wherein the first goods images and the second goods images correspond to different viewing angles respectively, and an image synthesis processing is performed according to the platform image and at least one of the first goods images and the second goods images to generate a synthesized image. The synthesized image includes a plurality of adjacent or partially overlapping image areas which correspond to at least many of the viewing angles. The image areas include a first and a second image areas. The first image area includes one of the first goods images or one of the second goods images. The second image area includes one of the first goods images or one of the second goods images.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang Hong LIN, Po Hsuan HSIAO, Guan Rong LIN, Yu-Chi LU
  • Publication number: 20220102147
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Patent number: 11201059
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20200105533
    Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Patent number: 10497571
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu Chen, Yu-Chi Lu, Chih-Pin Tsao, Shih-Hsun Chang
  • Publication number: 20190333769
    Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Yu CHEN, Yu-Chi LU, Chih-Pin TSAO, Shih-Hsun CHANG
  • Publication number: 20180167857
    Abstract: A handover method, system and user equipment are provided. The handover method includes establishing a voice call between a caller device and a callee device in a first network; detecting first-link performance between the caller device and the first network and detecting second-link performance between the caller device and a second network; detecting third-link performance between the callee device and the second network; and determining whether to turn over from the first network to the second network and start a standby call between the caller device and the callee device which has been established in the second network, according to the first-link performance, the second-link performance and the third-link performance, wherein the first network and the second network are respectively a circuit-switched network and a packet-switched network or respectively a packet-switched network and a circuit-switched network.
    Type: Application
    Filed: June 9, 2017
    Publication date: June 14, 2018
    Inventors: Tzi-Cker CHIUEH, Ching-Yao WANG, Yu-Chi LU
  • Patent number: 8486204
    Abstract: The hinge is made with a metal injection molding process from an alloy having at least: from 4 to 32 wt % Mn, from 16 to 37 wt % Cr, and from Fe that fills up the rest of the percentage.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 16, 2013
    Assignee: Shin Zu Shing Co., Ltd.
    Inventors: Yu-Chi Lu, Yu-Chan Hsieh, Shun-Tian Lin
  • Publication number: 20120120561
    Abstract: The hinge in accordance with the present invention is made with a metal injection molding process from an alloy having at least: from 4 to 32 wt % Mn, from 16 to 37 wt % Cr and Fe that fills up the rest percentage.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Applicant: SHIN ZU SHING CO., LTD.
    Inventors: Yu-Chi LU, Yu-Chan HSIEH, SHUN-TIAN LIN