Patents by Inventor Yu-Chi Sun
Yu-Chi Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6767837Abstract: A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C5F8 and CHF3, and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.Type: GrantFiled: March 5, 2003Date of Patent: July 27, 2004Assignee: Nanya Technology CorporationInventors: Yu-Chi Sun, Tse-Yao Huang
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Patent number: 6759300Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.Type: GrantFiled: April 28, 2003Date of Patent: July 6, 2004Assignee: Nanya Technology CorporationInventors: Chao-Wen Lay, Yu-Chi Sun, Tse-Yao Huang
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Publication number: 20040110342Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.Type: ApplicationFiled: April 28, 2003Publication date: June 10, 2004Applicant: Nanya Technology CorporationInventors: Chao-Wen Lay, Yu-Chi Sun, Tse-Yao Huang
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Publication number: 20040063317Abstract: A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C5F8 and CHF3, and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.Type: ApplicationFiled: March 5, 2003Publication date: April 1, 2004Applicant: Nanya Technology CorporationInventors: Yu-Chi Sun, Tse-Yao Huang
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Patent number: 6680254Abstract: A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first trench above the diffusion region. A second masking layer is formed to fill the first trench, and a hole is formed by removing a portion of the second masking layer above the diffusion region. A bit line contact is formed by removing a portion of the first insulating layer beneath the hole to expose the diffusion region. A bit line contact plug is formed by filling the bit line contact with a first conductive layer. The residual second masking layer and the first masking layer are removed to form a second trench. A bit line is formed by filling the second trench with a second conductive layer.Type: GrantFiled: August 24, 2001Date of Patent: January 20, 2004Assignee: Nanya Technology CorporationInventors: Yu-Chi Sun, Tse-Yao Huang
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Patent number: 6586324Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.Type: GrantFiled: January 25, 2002Date of Patent: July 1, 2003Assignee: Nanya Technology CorporationInventors: Tse-Yao Huang, Chih-Ching Lin, Yu-Chi Sun, Chang Rong Wu, Shing-Yih Shih
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Publication number: 20030082899Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.Type: ApplicationFiled: January 25, 2002Publication date: May 1, 2003Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Tse-Yao Huang, Chih-Ching Lin, Yu-Chi Sun, Chang Rong Wu, Shing-Yih Shih
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Publication number: 20030045099Abstract: A method of forming a self-aligned contact hole suitable for a semiconductor substrate having a pair of gate electrodes. First, a nitride etching stop layer is formed over the gate electrodes and the semiconductor substrate. Then, an oxide insulating layer is formed on the nitride etching stop layer, Next, the oxide insulating layer is plasma-etched by an etching gas containing C5F8 and CHF3 or C4F6 and CHF3 so as to form a self-aligned contact hole between the pair of gate electrode.Type: ApplicationFiled: December 13, 2001Publication date: March 6, 2003Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yu-Chi Sun, Tse-Yao Huang
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Publication number: 20020119649Abstract: A method of fabricating a bit line contact plug of a memory cell is disclosed. First, a semiconductor substrate having a transistor, comprising at least one diffused region is provided. A first insulating layer is formed on the substrate. A first masking layer is formed on the first insulating layer. The first masking layer and the first insulating layer are defined to form a first trench, which is above the diffusion region. A second masking layer is formed to fill the first trench. the materials of the first masking and the second masking are different. A hole is formed by removing the portion of the second masking layer, which is above the diffusion region. By using the first masking layer and the residual second masking layer as the mask, a bit line contact window is formed by removing a portion of the first insulating layer right beneath the hole until the surface of the diffusion region is exposed. A bit line contact plug is formed by forming a first conductive layer to fill the bit line contact window.Type: ApplicationFiled: August 24, 2001Publication date: August 29, 2002Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yu-Chi Sun, Tse-Yao Huang